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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
3
4# This example is actually equivalent as there's a sub in the loop, which is
5# then used by the add in the exit - making the vctp operands equivalent.
6
7--- |
8  define dso_local i32 @wrong_vctp_liveout(i16* nocapture readonly %a, i16* nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
9  entry:
10    %cmp9 = icmp eq i32 %N, 0
11    %0 = add i32 %N, 3
12    %1 = lshr i32 %0, 2
13    %2 = shl nuw i32 %1, 2
14    %3 = add i32 %2, -4
15    %4 = lshr i32 %3, 2
16    %5 = add nuw nsw i32 %4, 1
17    br i1 %cmp9, label %for.cond.cleanup, label %vector.ph
18
19  vector.ph:                                        ; preds = %entry
20    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
21    br label %vector.body
22
23  vector.body:                                      ; preds = %vector.body, %vector.ph
24    %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]
25    %lsr.iv18 = phi i16* [ %scevgep19, %vector.body ], [ %b, %vector.ph ]
26    %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
27    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]
28    %6 = phi i32 [ %N, %vector.ph ], [ %8, %vector.body ]
29    %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>*
30    %lsr.iv1820 = bitcast i16* %lsr.iv18 to <4 x i16>*
31    %7 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %6)
32    %8 = sub i32 %6, 4
33    %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %7, <4 x i16> undef)
34    %9 = sext <4 x i16> %wide.masked.load to <4 x i32>
35    %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1820, i32 2, <4 x i1> %7, <4 x i16> undef)
36    %10 = sext <4 x i16> %wide.masked.load14 to <4 x i32>
37    %11 = mul nsw <4 x i32> %10, %9
38    %12 = add <4 x i32> %11, %vec.phi
39    %scevgep = getelementptr i16, i16* %lsr.iv, i32 4
40    %scevgep19 = getelementptr i16, i16* %lsr.iv18, i32 4
41    %13 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)
42    %14 = icmp ne i32 %13, 0
43    %lsr.iv.next = add nsw i32 %lsr.iv1, -1
44    br i1 %14, label %vector.body, label %middle.block
45
46  middle.block:                                     ; preds = %vector.body
47    %15 = add i32 %8, 4
48    %16 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %15)
49    %17 = select <4 x i1> %16, <4 x i32> %12, <4 x i32> %vec.phi
50    %18 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %17)
51    br label %for.cond.cleanup
52
53  for.cond.cleanup:                                 ; preds = %middle.block, %entry
54    %res.0.lcssa = phi i32 [ 0, %entry ], [ %18, %middle.block ]
55    ret i32 %res.0.lcssa
56  }
57  declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
58  declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
59  declare i32 @llvm.start.loop.iterations.i32(i32)
60  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
61  declare <4 x i1> @llvm.arm.mve.vctp32(i32)
62
63...
64---
65name:            wrong_vctp_liveout
66alignment:       2
67exposesReturnsTwice: false
68legalized:       false
69regBankSelected: false
70selected:        false
71failedISel:      false
72tracksRegLiveness: true
73hasWinCFI:       false
74registers:       []
75liveins:
76  - { reg: '$r0', virtual-reg: '' }
77  - { reg: '$r1', virtual-reg: '' }
78  - { reg: '$r2', virtual-reg: '' }
79frameInfo:
80  isFrameAddressTaken: false
81  isReturnAddressTaken: false
82  hasStackMap:     false
83  hasPatchPoint:   false
84  stackSize:       8
85  offsetAdjustment: 0
86  maxAlignment:    4
87  adjustsStack:    false
88  hasCalls:        false
89  stackProtector:  ''
90  maxCallFrameSize: 0
91  cvBytesOfCalleeSavedRegisters: 0
92  hasOpaqueSPAdjustment: false
93  hasVAStart:      false
94  hasMustTailInVarArgFunc: false
95  localFrameSize:  0
96  savePoint:       ''
97  restorePoint:    ''
98fixedStack:      []
99stack:
100  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
101      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
102      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
103  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
104      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
105      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
106callSites:       []
107constants:       []
108machineFunctionInfo: {}
109body:             |
110  ; CHECK-LABEL: name: wrong_vctp_liveout
111  ; CHECK: bb.0.entry:
112  ; CHECK:   successors: %bb.1(0x80000000)
113  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
114  ; CHECK:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
115  ; CHECK:   t2IT 0, 4, implicit-def $itstate
116  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
117  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
118  ; CHECK: bb.1.vector.ph:
119  ; CHECK:   successors: %bb.2(0x80000000)
120  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
121  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
122  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
123  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
124  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
125  ; CHECK:   renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
126  ; CHECK:   renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
127  ; CHECK:   renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
128  ; CHECK:   renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
129  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
130  ; CHECK:   renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
131  ; CHECK:   dead $lr = t2DLS renamable $r12
132  ; CHECK:   $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
133  ; CHECK: bb.2.vector.body:
134  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
135  ; CHECK:   liveins: $q1, $r0, $r1, $r2, $r3
136  ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
137  ; CHECK:   $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
138  ; CHECK:   MVE_VPST 4, implicit $vpr
139  ; CHECK:   renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
140  ; CHECK:   renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
141  ; CHECK:   $lr = tMOVr $r3, 14 /* CC::al */, $noreg
142  ; CHECK:   renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
143  ; CHECK:   renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
144  ; CHECK:   renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
145  ; CHECK:   renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
146  ; CHECK:   dead $lr = t2LEUpdate killed renamable $lr, %bb.2
147  ; CHECK: bb.3.middle.block:
148  ; CHECK:   liveins: $q0, $q1, $r2
149  ; CHECK:   renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
150  ; CHECK:   renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg
151  ; CHECK:   renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr
152  ; CHECK:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
153  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
154  bb.0.entry:
155    successors: %bb.1(0x80000000)
156    liveins: $r0, $r1, $r2, $lr, $r7
157
158    tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
159    t2IT 0, 4, implicit-def $itstate
160    renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
161    tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
162
163  bb.1.vector.ph:
164    successors: %bb.2(0x80000000)
165    liveins: $r0, $r1, $r2, $lr, $r7
166
167    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
168    frame-setup CFI_INSTRUCTION def_cfa_offset 8
169    frame-setup CFI_INSTRUCTION offset $lr, -4
170    frame-setup CFI_INSTRUCTION offset $r7, -8
171    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
172    renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
173    renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
174    renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
175    renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
176    renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
177    $lr = t2DoLoopStart renamable $r12
178    $r3 = tMOVr killed $r12, 14, $noreg
179
180  bb.2.vector.body:
181    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
182    liveins: $q1, $r0, $r1, $r2, $r3
183
184    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
185    $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0
186    MVE_VPST 4, implicit $vpr
187    renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
188    renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
189    $lr = tMOVr $r3, 14, $noreg
190    renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
191    renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg
192    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
193    renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
194    renamable $lr = t2LoopDec killed renamable $lr, 1
195    t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
196    tB %bb.3, 14, $noreg
197
198  bb.3.middle.block:
199    liveins: $q0, $q1, $r2
200
201    renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14, $noreg
202    renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg
203    renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr
204    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
205    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
206
207...
208