1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+cdecp0 -mattr=+cdecp1 -verify-machineinstrs -o - %s | FileCheck %s 3; RUN: llc -mtriple=thumbebv8.1m.main -mattr=+cdecp0 -mattr=+cdecp1 -verify-machineinstrs -o - %s | FileCheck %s 4 5declare i32 @llvm.arm.cde.cx1(i32 immarg, i32 immarg) 6declare i32 @llvm.arm.cde.cx1a(i32 immarg, i32, i32 immarg) 7declare { i32, i32 } @llvm.arm.cde.cx1d(i32 immarg, i32 immarg) 8declare { i32, i32 } @llvm.arm.cde.cx1da(i32 immarg, i32, i32, i32 immarg) 9 10declare i32 @llvm.arm.cde.cx2(i32 immarg, i32, i32 immarg) 11declare i32 @llvm.arm.cde.cx2a(i32 immarg, i32, i32, i32 immarg) 12declare { i32, i32 } @llvm.arm.cde.cx2d(i32 immarg, i32, i32 immarg) 13declare { i32, i32 } @llvm.arm.cde.cx2da(i32 immarg, i32, i32, i32, i32 immarg) 14 15declare i32 @llvm.arm.cde.cx3(i32 immarg, i32, i32, i32 immarg) 16declare i32 @llvm.arm.cde.cx3a(i32 immarg, i32, i32, i32, i32 immarg) 17declare { i32, i32 } @llvm.arm.cde.cx3d(i32 immarg, i32, i32, i32 immarg) 18declare { i32, i32 } @llvm.arm.cde.cx3da(i32 immarg, i32, i32, i32, i32, i32 immarg) 19 20define arm_aapcs_vfpcc i32 @test_cx1() { 21; CHECK-LABEL: test_cx1: 22; CHECK: @ %bb.0: @ %entry 23; CHECK-NEXT: cx1 p0, r0, #123 24; CHECK-NEXT: bx lr 25entry: 26 %0 = call i32 @llvm.arm.cde.cx1(i32 0, i32 123) 27 ret i32 %0 28} 29 30define arm_aapcs_vfpcc i32 @test_cx1a(i32 %acc) { 31; CHECK-LABEL: test_cx1a: 32; CHECK: @ %bb.0: @ %entry 33; CHECK-NEXT: cx1a p0, r0, #345 34; CHECK-NEXT: bx lr 35entry: 36 %0 = call i32 @llvm.arm.cde.cx1a(i32 0, i32 %acc, i32 345) 37 ret i32 %0 38} 39 40define arm_aapcs_vfpcc i64 @test_cx1d() { 41; CHECK-LABEL: test_cx1d: 42; CHECK: @ %bb.0: @ %entry 43; CHECK-NEXT: cx1d p1, r0, r1, #567 44; CHECK-NEXT: bx lr 45entry: 46 %0 = call { i32, i32 } @llvm.arm.cde.cx1d(i32 1, i32 567) 47 %1 = extractvalue { i32, i32 } %0, 1 48 %2 = zext i32 %1 to i64 49 %3 = shl i64 %2, 32 50 %4 = extractvalue { i32, i32 } %0, 0 51 %5 = zext i32 %4 to i64 52 %6 = or i64 %3, %5 53 ret i64 %6 54} 55 56define arm_aapcs_vfpcc i64 @test_cx1da(i64 %acc) { 57; CHECK-LABEL: test_cx1da: 58; CHECK: @ %bb.0: @ %entry 59; CHECK-NEXT: @ kill: def $r1 killed $r1 killed $r0_r1 def $r0_r1 60; CHECK-NEXT: @ kill: def $r0 killed $r0 killed $r0_r1 def $r0_r1 61; CHECK-NEXT: cx1da p0, r0, r1, #789 62; CHECK-NEXT: bx lr 63entry: 64 %0 = lshr i64 %acc, 32 65 %1 = trunc i64 %0 to i32 66 %2 = trunc i64 %acc to i32 67 %3 = call { i32, i32 } @llvm.arm.cde.cx1da(i32 0, i32 %2, i32 %1, i32 789) 68 %4 = extractvalue { i32, i32 } %3, 1 69 %5 = zext i32 %4 to i64 70 %6 = shl i64 %5, 32 71 %7 = extractvalue { i32, i32 } %3, 0 72 %8 = zext i32 %7 to i64 73 %9 = or i64 %6, %8 74 ret i64 %9 75} 76 77define arm_aapcs_vfpcc i32 @test_cx2(i32 %n) { 78; CHECK-LABEL: test_cx2: 79; CHECK: @ %bb.0: @ %entry 80; CHECK-NEXT: cx2 p0, r0, r0, #11 81; CHECK-NEXT: bx lr 82entry: 83 %0 = call i32 @llvm.arm.cde.cx2(i32 0, i32 %n, i32 11) 84 ret i32 %0 85} 86 87define arm_aapcs_vfpcc i32 @test_cx2a(i32 %acc, i32 %n) { 88; CHECK-LABEL: test_cx2a: 89; CHECK: @ %bb.0: @ %entry 90; CHECK-NEXT: cx2a p1, r0, r1, #22 91; CHECK-NEXT: bx lr 92entry: 93 %0 = call i32 @llvm.arm.cde.cx2a(i32 1, i32 %acc, i32 %n, i32 22) 94 ret i32 %0 95} 96 97define arm_aapcs_vfpcc i64 @test_cx2d(i32 %n) #0 { 98; CHECK-LABEL: test_cx2d: 99; CHECK: @ %bb.0: @ %entry 100; CHECK-NEXT: cx2d p1, r0, r1, r0, #33 101; CHECK-NEXT: bx lr 102entry: 103 %0 = call { i32, i32 } @llvm.arm.cde.cx2d(i32 1, i32 %n, i32 33) 104 %1 = extractvalue { i32, i32 } %0, 1 105 %2 = zext i32 %1 to i64 106 %3 = shl i64 %2, 32 107 %4 = extractvalue { i32, i32 } %0, 0 108 %5 = zext i32 %4 to i64 109 %6 = or i64 %3, %5 110 ret i64 %6 111} 112 113define arm_aapcs_vfpcc i64 @test_cx2da(i64 %acc, i32 %n) { 114; CHECK-LABEL: test_cx2da: 115; CHECK: @ %bb.0: @ %entry 116; CHECK-NEXT: @ kill: def $r1 killed $r1 killed $r0_r1 def $r0_r1 117; CHECK-NEXT: @ kill: def $r0 killed $r0 killed $r0_r1 def $r0_r1 118; CHECK-NEXT: cx2da p0, r0, r1, r2, #44 119; CHECK-NEXT: bx lr 120entry: 121 %0 = lshr i64 %acc, 32 122 %1 = trunc i64 %0 to i32 123 %2 = trunc i64 %acc to i32 124 %3 = call { i32, i32 } @llvm.arm.cde.cx2da(i32 0, i32 %2, i32 %1, i32 %n, i32 44) 125 %4 = extractvalue { i32, i32 } %3, 1 126 %5 = zext i32 %4 to i64 127 %6 = shl i64 %5, 32 128 %7 = extractvalue { i32, i32 } %3, 0 129 %8 = zext i32 %7 to i64 130 %9 = or i64 %6, %8 131 ret i64 %9 132} 133 134define arm_aapcs_vfpcc i32 @test_cx3(i32 %n, i32 %m) { 135; CHECK-LABEL: test_cx3: 136; CHECK: @ %bb.0: @ %entry 137; CHECK-NEXT: cx3 p0, r0, r0, r1, #1 138; CHECK-NEXT: bx lr 139entry: 140 %0 = call i32 @llvm.arm.cde.cx3(i32 0, i32 %n, i32 %m, i32 1) 141 ret i32 %0 142} 143 144define arm_aapcs_vfpcc i32 @test_cx3a(i32 %acc, i32 %n, i32 %m) { 145; CHECK-LABEL: test_cx3a: 146; CHECK: @ %bb.0: @ %entry 147; CHECK-NEXT: cx3a p1, r0, r1, r2, #2 148; CHECK-NEXT: bx lr 149entry: 150 %0 = call i32 @llvm.arm.cde.cx3a(i32 1, i32 %acc, i32 %n, i32 %m, i32 2) 151 ret i32 %0 152} 153 154define arm_aapcs_vfpcc i64 @test_cx3d(i32 %n, i32 %m) { 155; CHECK-LABEL: test_cx3d: 156; CHECK: @ %bb.0: @ %entry 157; CHECK-NEXT: cx3d p1, r0, r1, r0, r1, #3 158; CHECK-NEXT: bx lr 159entry: 160 %0 = call { i32, i32 } @llvm.arm.cde.cx3d(i32 1, i32 %n, i32 %m, i32 3) 161 %1 = extractvalue { i32, i32 } %0, 1 162 %2 = zext i32 %1 to i64 163 %3 = shl i64 %2, 32 164 %4 = extractvalue { i32, i32 } %0, 0 165 %5 = zext i32 %4 to i64 166 %6 = or i64 %3, %5 167 ret i64 %6 168} 169 170define arm_aapcs_vfpcc i64 @test_cx3da(i64 %acc, i32 %n, i32 %m) { 171; CHECK-LABEL: test_cx3da: 172; CHECK: @ %bb.0: @ %entry 173; CHECK-NEXT: @ kill: def $r1 killed $r1 killed $r0_r1 def $r0_r1 174; CHECK-NEXT: @ kill: def $r0 killed $r0 killed $r0_r1 def $r0_r1 175; CHECK-NEXT: cx3da p0, r0, r1, r2, r3, #4 176; CHECK-NEXT: bx lr 177entry: 178 %0 = lshr i64 %acc, 32 179 %1 = trunc i64 %0 to i32 180 %2 = trunc i64 %acc to i32 181 %3 = call { i32, i32 } @llvm.arm.cde.cx3da(i32 0, i32 %2, i32 %1, i32 %n, i32 %m, i32 4) 182 %4 = extractvalue { i32, i32 } %3, 1 183 %5 = zext i32 %4 to i64 184 %6 = shl i64 %5, 32 185 %7 = extractvalue { i32, i32 } %3, 0 186 %8 = zext i32 %7 to i64 187 %9 = or i64 %6, %8 188 ret i64 %9 189} 190