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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; NOTE: Assertions have been autoenerated by utils/update_llc_test_checks.py
3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
4
5define arm_aapcs_vfpcc <2 x i64> @ctpop_2i64_t(<2 x i64> %src){
6; CHECK-LABEL: ctpop_2i64_t:
7; CHECK:       @ %bb.0: @ %entry
8; CHECK-NEXT:    .save {r4, lr}
9; CHECK-NEXT:    push {r4, lr}
10; CHECK-NEXT:    vmov r0, s3
11; CHECK-NEXT:    mov.w r1, #1431655765
12; CHECK-NEXT:    mov.w lr, #858993459
13; CHECK-NEXT:    mov.w r4, #16843009
14; CHECK-NEXT:    and.w r2, r1, r0, lsr #1
15; CHECK-NEXT:    subs r0, r0, r2
16; CHECK-NEXT:    and.w r3, lr, r0, lsr #2
17; CHECK-NEXT:    bic r0, r0, #-858993460
18; CHECK-NEXT:    add r0, r3
19; CHECK-NEXT:    vmov r3, s2
20; CHECK-NEXT:    add.w r0, r0, r0, lsr #4
21; CHECK-NEXT:    bic r12, r0, #-252645136
22; CHECK-NEXT:    and.w r0, r1, r3, lsr #1
23; CHECK-NEXT:    subs r0, r3, r0
24; CHECK-NEXT:    and.w r3, lr, r0, lsr #2
25; CHECK-NEXT:    bic r0, r0, #-858993460
26; CHECK-NEXT:    add r0, r3
27; CHECK-NEXT:    vmov r3, s0
28; CHECK-NEXT:    add.w r0, r0, r0, lsr #4
29; CHECK-NEXT:    bic r0, r0, #-252645136
30; CHECK-NEXT:    muls r0, r4, r0
31; CHECK-NEXT:    lsrs r0, r0, #24
32; CHECK-NEXT:    and.w r2, r1, r3, lsr #1
33; CHECK-NEXT:    subs r2, r3, r2
34; CHECK-NEXT:    and.w r3, lr, r2, lsr #2
35; CHECK-NEXT:    bic r2, r2, #-858993460
36; CHECK-NEXT:    add r2, r3
37; CHECK-NEXT:    vmov r3, s1
38; CHECK-NEXT:    vldr s1, .LCPI0_0
39; CHECK-NEXT:    add.w r2, r2, r2, lsr #4
40; CHECK-NEXT:    bic r2, r2, #-252645136
41; CHECK-NEXT:    muls r2, r4, r2
42; CHECK-NEXT:    lsrs r2, r2, #24
43; CHECK-NEXT:    and.w r1, r1, r3, lsr #1
44; CHECK-NEXT:    subs r1, r3, r1
45; CHECK-NEXT:    and.w r3, lr, r1, lsr #2
46; CHECK-NEXT:    bic r1, r1, #-858993460
47; CHECK-NEXT:    add r1, r3
48; CHECK-NEXT:    mul r3, r12, r4
49; CHECK-NEXT:    add.w r1, r1, r1, lsr #4
50; CHECK-NEXT:    bic r1, r1, #-252645136
51; CHECK-NEXT:    muls r1, r4, r1
52; CHECK-NEXT:    add.w r0, r0, r3, lsr #24
53; CHECK-NEXT:    vmov s2, r0
54; CHECK-NEXT:    add.w r0, r2, r1, lsr #24
55; CHECK-NEXT:    vmov s0, r0
56; CHECK-NEXT:    vmov.f32 s3, s1
57; CHECK-NEXT:    pop {r4, pc}
58; CHECK-NEXT:    .p2align 2
59; CHECK-NEXT:  @ %bb.1:
60; CHECK-NEXT:  .LCPI0_0:
61; CHECK-NEXT:    .long 0x00000000 @ float 0
62entry:
63  %0 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %src)
64  ret <2 x i64> %0
65}
66
67define arm_aapcs_vfpcc <4 x i32> @ctpop_4i32_t(<4 x i32> %src){
68; CHECK-LABEL: ctpop_4i32_t:
69; CHECK:       @ %bb.0: @ %entry
70; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
71; CHECK-NEXT:    vpush {d8, d9, d10, d11}
72; CHECK-NEXT:    vmov.i8 q4, #0x55
73; CHECK-NEXT:    vshr.u32 q5, q0, #1
74; CHECK-NEXT:    vand q4, q5, q4
75; CHECK-NEXT:    vmov.i8 q3, #0x33
76; CHECK-NEXT:    vsub.i32 q0, q0, q4
77; CHECK-NEXT:    vmov.i8 q2, #0xf
78; CHECK-NEXT:    vshr.u32 q4, q0, #2
79; CHECK-NEXT:    vand q0, q0, q3
80; CHECK-NEXT:    vand q4, q4, q3
81; CHECK-NEXT:    vmov.i8 q1, #0x1
82; CHECK-NEXT:    vadd.i32 q0, q0, q4
83; CHECK-NEXT:    vshr.u32 q3, q0, #4
84; CHECK-NEXT:    vadd.i32 q0, q0, q3
85; CHECK-NEXT:    vand q0, q0, q2
86; CHECK-NEXT:    vmul.i32 q0, q0, q1
87; CHECK-NEXT:    vshr.u32 q0, q0, #24
88; CHECK-NEXT:    vpop {d8, d9, d10, d11}
89; CHECK-NEXT:    bx lr
90entry:
91  %0 = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %src)
92  ret <4 x i32> %0
93}
94
95define arm_aapcs_vfpcc <8 x i16> @ctpop_8i16_t(<8 x i16> %src){
96; CHECK-LABEL: ctpop_8i16_t:
97; CHECK:       @ %bb.0: @ %entry
98; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
99; CHECK-NEXT:    vpush {d8, d9, d10, d11}
100; CHECK-NEXT:    vmov.i8 q4, #0x55
101; CHECK-NEXT:    vshr.u16 q5, q0, #1
102; CHECK-NEXT:    vand q4, q5, q4
103; CHECK-NEXT:    vmov.i8 q3, #0x33
104; CHECK-NEXT:    vsub.i16 q0, q0, q4
105; CHECK-NEXT:    vmov.i8 q2, #0xf
106; CHECK-NEXT:    vshr.u16 q4, q0, #2
107; CHECK-NEXT:    vand q0, q0, q3
108; CHECK-NEXT:    vand q4, q4, q3
109; CHECK-NEXT:    vmov.i8 q1, #0x1
110; CHECK-NEXT:    vadd.i16 q0, q0, q4
111; CHECK-NEXT:    vshr.u16 q3, q0, #4
112; CHECK-NEXT:    vadd.i16 q0, q0, q3
113; CHECK-NEXT:    vand q0, q0, q2
114; CHECK-NEXT:    vmul.i16 q0, q0, q1
115; CHECK-NEXT:    vshr.u16 q0, q0, #8
116; CHECK-NEXT:    vpop {d8, d9, d10, d11}
117; CHECK-NEXT:    bx lr
118entry:
119  %0 = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %src)
120  ret <8 x i16> %0
121}
122
123define arm_aapcs_vfpcc <16 x i8> @ctpop_16i8_t(<16 x i8> %src){
124; CHECK-LABEL: ctpop_16i8_t:
125; CHECK:       @ %bb.0: @ %entry
126; CHECK-NEXT:    .vsave {d8, d9}
127; CHECK-NEXT:    vpush {d8, d9}
128; CHECK-NEXT:    vmov.i8 q3, #0x55
129; CHECK-NEXT:    vshr.u8 q4, q0, #1
130; CHECK-NEXT:    vand q3, q4, q3
131; CHECK-NEXT:    vmov.i8 q2, #0x33
132; CHECK-NEXT:    vsub.i8 q0, q0, q3
133; CHECK-NEXT:    vmov.i8 q1, #0xf
134; CHECK-NEXT:    vshr.u8 q3, q0, #2
135; CHECK-NEXT:    vand q0, q0, q2
136; CHECK-NEXT:    vand q3, q3, q2
137; CHECK-NEXT:    vadd.i8 q0, q0, q3
138; CHECK-NEXT:    vshr.u8 q2, q0, #4
139; CHECK-NEXT:    vadd.i8 q0, q0, q2
140; CHECK-NEXT:    vand q0, q0, q1
141; CHECK-NEXT:    vpop {d8, d9}
142; CHECK-NEXT:    bx lr
143entry:
144  %0 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %src)
145  ret <16 x i8> %0
146}
147
148declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
149declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
150declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>)
151declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)
152