1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s 3 4declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) 5declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) 6declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) 7 8declare i32 @llvm.arm.mve.vabav.v16i8(i32, i32, <16 x i8>, <16 x i8>) 9declare i32 @llvm.arm.mve.vabav.v8i16(i32, i32, <8 x i16>, <8 x i16>) 10declare i32 @llvm.arm.mve.vabav.v4i32(i32, i32, <4 x i32>, <4 x i32>) 11 12declare i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i1>) 13declare i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i1>) 14declare i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i1>) 15 16define arm_aapcs_vfpcc i32 @test_vabavq_s8(i32 %a, <16 x i8> %b, <16 x i8> %c) { 17; CHECK-LABEL: test_vabavq_s8: 18; CHECK: @ %bb.0: @ %entry 19; CHECK-NEXT: vabav.s8 r0, q0, q1 20; CHECK-NEXT: bx lr 21entry: 22 %0 = call i32 @llvm.arm.mve.vabav.v16i8(i32 0, i32 %a, <16 x i8> %b, <16 x i8> %c) 23 ret i32 %0 24} 25 26define arm_aapcs_vfpcc i32 @test_vabavq_s16(i32 %a, <8 x i16> %b, <8 x i16> %c) { 27; CHECK-LABEL: test_vabavq_s16: 28; CHECK: @ %bb.0: @ %entry 29; CHECK-NEXT: vabav.s16 r0, q0, q1 30; CHECK-NEXT: bx lr 31entry: 32 %0 = call i32 @llvm.arm.mve.vabav.v8i16(i32 0, i32 %a, <8 x i16> %b, <8 x i16> %c) 33 ret i32 %0 34} 35 36define arm_aapcs_vfpcc i32 @test_vabavq_s32(i32 %a, <4 x i32> %b, <4 x i32> %c) { 37; CHECK-LABEL: test_vabavq_s32: 38; CHECK: @ %bb.0: @ %entry 39; CHECK-NEXT: vabav.s32 r0, q0, q1 40; CHECK-NEXT: bx lr 41entry: 42 %0 = call i32 @llvm.arm.mve.vabav.v4i32(i32 0, i32 %a, <4 x i32> %b, <4 x i32> %c) 43 ret i32 %0 44} 45 46define arm_aapcs_vfpcc i32 @test_vabavq_u8(i32 %a, <16 x i8> %b, <16 x i8> %c) { 47; CHECK-LABEL: test_vabavq_u8: 48; CHECK: @ %bb.0: @ %entry 49; CHECK-NEXT: vabav.u8 r0, q0, q1 50; CHECK-NEXT: bx lr 51entry: 52 %0 = call i32 @llvm.arm.mve.vabav.v16i8(i32 1, i32 %a, <16 x i8> %b, <16 x i8> %c) 53 ret i32 %0 54} 55 56define arm_aapcs_vfpcc i32 @test_vabavq_u16(i32 %a, <8 x i16> %b, <8 x i16> %c) { 57; CHECK-LABEL: test_vabavq_u16: 58; CHECK: @ %bb.0: @ %entry 59; CHECK-NEXT: vabav.u16 r0, q0, q1 60; CHECK-NEXT: bx lr 61entry: 62 %0 = call i32 @llvm.arm.mve.vabav.v8i16(i32 1, i32 %a, <8 x i16> %b, <8 x i16> %c) 63 ret i32 %0 64} 65 66define arm_aapcs_vfpcc i32 @test_vabavq_u32(i32 %a, <4 x i32> %b, <4 x i32> %c) { 67; CHECK-LABEL: test_vabavq_u32: 68; CHECK: @ %bb.0: @ %entry 69; CHECK-NEXT: vabav.u32 r0, q0, q1 70; CHECK-NEXT: bx lr 71entry: 72 %0 = call i32 @llvm.arm.mve.vabav.v4i32(i32 1, i32 %a, <4 x i32> %b, <4 x i32> %c) 73 ret i32 %0 74} 75 76define arm_aapcs_vfpcc i32 @test_vabavq_p_s8(i32 %a, <16 x i8> %b, <16 x i8> %c, i16 zeroext %p) { 77; CHECK-LABEL: test_vabavq_p_s8: 78; CHECK: @ %bb.0: @ %entry 79; CHECK-NEXT: vmsr p0, r1 80; CHECK-NEXT: vpst 81; CHECK-NEXT: vabavt.s8 r0, q0, q1 82; CHECK-NEXT: bx lr 83entry: 84 %0 = zext i16 %p to i32 85 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) 86 %2 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 0, i32 %a, <16 x i8> %b, <16 x i8> %c, <16 x i1> %1) 87 ret i32 %2 88} 89 90define arm_aapcs_vfpcc i32 @test_vabavq_p_s16(i32 %a, <8 x i16> %b, <8 x i16> %c, i16 zeroext %p) { 91; CHECK-LABEL: test_vabavq_p_s16: 92; CHECK: @ %bb.0: @ %entry 93; CHECK-NEXT: vmsr p0, r1 94; CHECK-NEXT: vpst 95; CHECK-NEXT: vabavt.s16 r0, q0, q1 96; CHECK-NEXT: bx lr 97entry: 98 %0 = zext i16 %p to i32 99 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 100 %2 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 0, i32 %a, <8 x i16> %b, <8 x i16> %c, <8 x i1> %1) 101 ret i32 %2 102} 103 104define arm_aapcs_vfpcc i32 @test_vabavq_p_s32(i32 %a, <4 x i32> %b, <4 x i32> %c, i16 zeroext %p) { 105; CHECK-LABEL: test_vabavq_p_s32: 106; CHECK: @ %bb.0: @ %entry 107; CHECK-NEXT: vmsr p0, r1 108; CHECK-NEXT: vpst 109; CHECK-NEXT: vabavt.s32 r0, q0, q1 110; CHECK-NEXT: bx lr 111entry: 112 %0 = zext i16 %p to i32 113 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 114 %2 = call i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32 0, i32 %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %1) 115 ret i32 %2 116} 117 118define arm_aapcs_vfpcc i32 @test_vabavq_p_u8(i32 %a, <16 x i8> %b, <16 x i8> %c, i16 zeroext %p) { 119; CHECK-LABEL: test_vabavq_p_u8: 120; CHECK: @ %bb.0: @ %entry 121; CHECK-NEXT: vmsr p0, r1 122; CHECK-NEXT: vpst 123; CHECK-NEXT: vabavt.u8 r0, q0, q1 124; CHECK-NEXT: bx lr 125entry: 126 %0 = zext i16 %p to i32 127 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) 128 %2 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 1, i32 %a, <16 x i8> %b, <16 x i8> %c, <16 x i1> %1) 129 ret i32 %2 130} 131 132define arm_aapcs_vfpcc i32 @test_vabavq_p_u16(i32 %a, <8 x i16> %b, <8 x i16> %c, i16 zeroext %p) { 133; CHECK-LABEL: test_vabavq_p_u16: 134; CHECK: @ %bb.0: @ %entry 135; CHECK-NEXT: vmsr p0, r1 136; CHECK-NEXT: vpst 137; CHECK-NEXT: vabavt.u16 r0, q0, q1 138; CHECK-NEXT: bx lr 139entry: 140 %0 = zext i16 %p to i32 141 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 142 %2 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 1, i32 %a, <8 x i16> %b, <8 x i16> %c, <8 x i1> %1) 143 ret i32 %2 144} 145 146define arm_aapcs_vfpcc i32 @test_vabavq_p_u32(i32 %a, <4 x i32> %b, <4 x i32> %c, i16 zeroext %p) { 147; CHECK-LABEL: test_vabavq_p_u32: 148; CHECK: @ %bb.0: @ %entry 149; CHECK-NEXT: vmsr p0, r1 150; CHECK-NEXT: vpst 151; CHECK-NEXT: vabavt.u32 r0, q0, q1 152; CHECK-NEXT: bx lr 153entry: 154 %0 = zext i16 %p to i32 155 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 156 %2 = call i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32 1, i32 %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %1) 157 ret i32 %2 158} 159