1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s 3 4declare <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half>, i32) 5declare <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32>, i32) 6declare <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>) 7declare <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>) 8declare <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>) 9declare <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>) 10 11declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) 12declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) 13declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) 14 15define arm_aapcs_vfpcc <4 x i32> @test_vbrsrq_n_u32(<4 x i32> %a, i32 %b) { 16; CHECK-LABEL: test_vbrsrq_n_u32: 17; CHECK: @ %bb.0: @ %entry 18; CHECK-NEXT: vbrsr.32 q0, q0, r0 19; CHECK-NEXT: bx lr 20entry: 21 %0 = call <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32> %a, i32 %b) 22 ret <4 x i32> %0 23} 24 25define arm_aapcs_vfpcc <8 x half> @test_vbrsrq_n_f16(<8 x half> %a, i32 %b) { 26; CHECK-LABEL: test_vbrsrq_n_f16: 27; CHECK: @ %bb.0: @ %entry 28; CHECK-NEXT: vbrsr.16 q0, q0, r0 29; CHECK-NEXT: bx lr 30entry: 31 %0 = call <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half> %a, i32 %b) 32 ret <8 x half> %0 33} 34 35define arm_aapcs_vfpcc <16 x i8> @test_vbrsrq_m_n_s8(<16 x i8> %inactive, <16 x i8> %a, i32 %b, i16 zeroext %p) { 36; CHECK-LABEL: test_vbrsrq_m_n_s8: 37; CHECK: @ %bb.0: @ %entry 38; CHECK-NEXT: vmsr p0, r1 39; CHECK-NEXT: vpst 40; CHECK-NEXT: vbrsrt.8 q0, q1, r0 41; CHECK-NEXT: bx lr 42entry: 43 %0 = zext i16 %p to i32 44 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) 45 %2 = call <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, i32 %b, <16 x i1> %1) 46 ret <16 x i8> %2 47} 48 49define arm_aapcs_vfpcc <4 x float> @test_vbrsrq_m_n_f32(<4 x float> %inactive, <4 x float> %a, i32 %b, i16 zeroext %p) { 50; CHECK-LABEL: test_vbrsrq_m_n_f32: 51; CHECK: @ %bb.0: @ %entry 52; CHECK-NEXT: vmsr p0, r1 53; CHECK-NEXT: vpst 54; CHECK-NEXT: vbrsrt.32 q0, q1, r0 55; CHECK-NEXT: bx lr 56entry: 57 %0 = zext i16 %p to i32 58 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 59 %2 = call <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float> %inactive, <4 x float> %a, i32 %b, <4 x i1> %1) 60 ret <4 x float> %2 61} 62 63define arm_aapcs_vfpcc <8 x i16> @test_vbrsrq_x_n_u16(<8 x i16> %a, i32 %b, i16 zeroext %p) { 64; CHECK-LABEL: test_vbrsrq_x_n_u16: 65; CHECK: @ %bb.0: @ %entry 66; CHECK-NEXT: vmsr p0, r1 67; CHECK-NEXT: vpst 68; CHECK-NEXT: vbrsrt.16 q0, q0, r0 69; CHECK-NEXT: bx lr 70entry: 71 %0 = zext i16 %p to i32 72 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 73 %2 = call <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16> undef, <8 x i16> %a, i32 %b, <8 x i1> %1) 74 ret <8 x i16> %2 75} 76 77define arm_aapcs_vfpcc <8 x half> @test_vbrsrq_x_n_f16(<8 x half> %a, i32 %b, i16 zeroext %p) { 78; CHECK-LABEL: test_vbrsrq_x_n_f16: 79; CHECK: @ %bb.0: @ %entry 80; CHECK-NEXT: vmsr p0, r1 81; CHECK-NEXT: vpst 82; CHECK-NEXT: vbrsrt.16 q0, q0, r0 83; CHECK-NEXT: bx lr 84entry: 85 %0 = zext i16 %p to i32 86 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 87 %2 = call <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half> undef, <8 x half> %a, i32 %b, <8 x i1> %1) 88 ret <8 x half> %2 89} 90