1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s 3 4define arm_aapcs_vfpcc <16 x i8> @test_veorq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 5; CHECK-LABEL: test_veorq_u8: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: veor q0, q1, q0 8; CHECK-NEXT: bx lr 9entry: 10 %0 = xor <16 x i8> %b, %a 11 ret <16 x i8> %0 12} 13 14define arm_aapcs_vfpcc <8 x i16> @test_veorq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 { 15; CHECK-LABEL: test_veorq_s16: 16; CHECK: @ %bb.0: @ %entry 17; CHECK-NEXT: veor q0, q1, q0 18; CHECK-NEXT: bx lr 19entry: 20 %0 = xor <8 x i16> %b, %a 21 ret <8 x i16> %0 22} 23 24define arm_aapcs_vfpcc <4 x i32> @test_veorq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 { 25; CHECK-LABEL: test_veorq_u32: 26; CHECK: @ %bb.0: @ %entry 27; CHECK-NEXT: veor q0, q1, q0 28; CHECK-NEXT: bx lr 29entry: 30 %0 = xor <4 x i32> %b, %a 31 ret <4 x i32> %0 32} 33 34define arm_aapcs_vfpcc <4 x float> @test_veorq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 { 35; CHECK-LABEL: test_veorq_f32: 36; CHECK: @ %bb.0: @ %entry 37; CHECK-NEXT: veor q0, q1, q0 38; CHECK-NEXT: bx lr 39entry: 40 %0 = bitcast <4 x float> %a to <4 x i32> 41 %1 = bitcast <4 x float> %b to <4 x i32> 42 %2 = xor <4 x i32> %1, %0 43 %3 = bitcast <4 x i32> %2 to <4 x float> 44 ret <4 x float> %3 45} 46 47define arm_aapcs_vfpcc <16 x i8> @test_veorq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 { 48; CHECK-LABEL: test_veorq_m_s8: 49; CHECK: @ %bb.0: @ %entry 50; CHECK-NEXT: vmsr p0, r0 51; CHECK-NEXT: vpst 52; CHECK-NEXT: veort q0, q1, q2 53; CHECK-NEXT: bx lr 54entry: 55 %0 = zext i16 %p to i32 56 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) 57 %2 = tail call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive) 58 ret <16 x i8> %2 59} 60 61declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 62 63declare <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #2 64 65define arm_aapcs_vfpcc <8 x i16> @test_veorq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 { 66; CHECK-LABEL: test_veorq_m_u16: 67; CHECK: @ %bb.0: @ %entry 68; CHECK-NEXT: vmsr p0, r0 69; CHECK-NEXT: vpst 70; CHECK-NEXT: veort q0, q1, q2 71; CHECK-NEXT: bx lr 72entry: 73 %0 = zext i16 %p to i32 74 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 75 %2 = tail call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive) 76 ret <8 x i16> %2 77} 78 79declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 80 81declare <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2 82 83define arm_aapcs_vfpcc <4 x i32> @test_veorq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 { 84; CHECK-LABEL: test_veorq_m_s32: 85; CHECK: @ %bb.0: @ %entry 86; CHECK-NEXT: vmsr p0, r0 87; CHECK-NEXT: vpst 88; CHECK-NEXT: veort q0, q1, q2 89; CHECK-NEXT: bx lr 90entry: 91 %0 = zext i16 %p to i32 92 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 93 %2 = tail call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive) 94 ret <4 x i32> %2 95} 96 97declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 98 99declare <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2 100 101define arm_aapcs_vfpcc <8 x half> @test_veorq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #1 { 102; CHECK-LABEL: test_veorq_m_f16: 103; CHECK: @ %bb.0: @ %entry 104; CHECK-NEXT: vmsr p0, r0 105; CHECK-NEXT: vpst 106; CHECK-NEXT: veort q0, q1, q2 107; CHECK-NEXT: bx lr 108entry: 109 %0 = bitcast <8 x half> %a to <8 x i16> 110 %1 = bitcast <8 x half> %b to <8 x i16> 111 %2 = zext i16 %p to i32 112 %3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) 113 %4 = bitcast <8 x half> %inactive to <8 x i16> 114 %5 = tail call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %3, <8 x i16> %4) 115 %6 = bitcast <8 x i16> %5 to <8 x half> 116 ret <8 x half> %6 117} 118 119define arm_aapcs_vfpcc <16 x i8> @test_veorq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 { 120; CHECK-LABEL: test_veorq_x_u8: 121; CHECK: @ %bb.0: @ %entry 122; CHECK-NEXT: vmsr p0, r0 123; CHECK-NEXT: vpst 124; CHECK-NEXT: veort q0, q0, q1 125; CHECK-NEXT: bx lr 126entry: 127 %0 = zext i16 %p to i32 128 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) 129 %2 = tail call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef) 130 ret <16 x i8> %2 131} 132 133define arm_aapcs_vfpcc <8 x i16> @test_veorq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 { 134; CHECK-LABEL: test_veorq_x_s16: 135; CHECK: @ %bb.0: @ %entry 136; CHECK-NEXT: vmsr p0, r0 137; CHECK-NEXT: vpst 138; CHECK-NEXT: veort q0, q0, q1 139; CHECK-NEXT: bx lr 140entry: 141 %0 = zext i16 %p to i32 142 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 143 %2 = tail call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef) 144 ret <8 x i16> %2 145} 146 147define arm_aapcs_vfpcc <4 x i32> @test_veorq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 { 148; CHECK-LABEL: test_veorq_x_u32: 149; CHECK: @ %bb.0: @ %entry 150; CHECK-NEXT: vmsr p0, r0 151; CHECK-NEXT: vpst 152; CHECK-NEXT: veort q0, q0, q1 153; CHECK-NEXT: bx lr 154entry: 155 %0 = zext i16 %p to i32 156 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 157 %2 = tail call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef) 158 ret <4 x i32> %2 159} 160 161define arm_aapcs_vfpcc <4 x float> @test_veorq_m_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 { 162; CHECK-LABEL: test_veorq_m_f32: 163; CHECK: @ %bb.0: @ %entry 164; CHECK-NEXT: vmsr p0, r0 165; CHECK-NEXT: vpst 166; CHECK-NEXT: veort q0, q0, q1 167; CHECK-NEXT: bx lr 168entry: 169 %0 = bitcast <4 x float> %a to <4 x i32> 170 %1 = bitcast <4 x float> %b to <4 x i32> 171 %2 = zext i16 %p to i32 172 %3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) 173 %4 = tail call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %3, <4 x i32> undef) 174 %5 = bitcast <4 x i32> %4 to <4 x float> 175 ret <4 x float> %5 176} 177 178