1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s 3 4define arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_s8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 5; CHECK-LABEL: test_vmaxaq_s8: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vmaxa.s8 q0, q1 8; CHECK-NEXT: bx lr 9entry: 10 %0 = icmp slt <16 x i8> %b, zeroinitializer 11 %1 = sub <16 x i8> zeroinitializer, %b 12 %2 = select <16 x i1> %0, <16 x i8> %1, <16 x i8> %b 13 %3 = icmp ugt <16 x i8> %2, %a 14 %4 = select <16 x i1> %3, <16 x i8> %2, <16 x i8> %a 15 ret <16 x i8> %4 16} 17 18define arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 { 19; CHECK-LABEL: test_vmaxaq_s16: 20; CHECK: @ %bb.0: @ %entry 21; CHECK-NEXT: vmaxa.s16 q0, q1 22; CHECK-NEXT: bx lr 23entry: 24 %0 = icmp slt <8 x i16> %b, zeroinitializer 25 %1 = sub <8 x i16> zeroinitializer, %b 26 %2 = select <8 x i1> %0, <8 x i16> %1, <8 x i16> %b 27 %3 = icmp ugt <8 x i16> %2, %a 28 %4 = select <8 x i1> %3, <8 x i16> %2, <8 x i16> %a 29 ret <8 x i16> %4 30} 31 32define arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_s32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 { 33; CHECK-LABEL: test_vmaxaq_s32: 34; CHECK: @ %bb.0: @ %entry 35; CHECK-NEXT: vmaxa.s32 q0, q1 36; CHECK-NEXT: bx lr 37entry: 38 %0 = icmp slt <4 x i32> %b, zeroinitializer 39 %1 = sub <4 x i32> zeroinitializer, %b 40 %2 = select <4 x i1> %0, <4 x i32> %1, <4 x i32> %b 41 %3 = icmp ugt <4 x i32> %2, %a 42 %4 = select <4 x i1> %3, <4 x i32> %2, <4 x i32> %a 43 ret <4 x i32> %4 44} 45 46define arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_m_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 { 47; CHECK-LABEL: test_vmaxaq_m_s8: 48; CHECK: @ %bb.0: @ %entry 49; CHECK-NEXT: vmsr p0, r0 50; CHECK-NEXT: vpst 51; CHECK-NEXT: vmaxat.s8 q0, q1 52; CHECK-NEXT: bx lr 53entry: 54 %0 = zext i16 %p to i32 55 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) 56 %2 = tail call <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1) 57 ret <16 x i8> %2 58} 59 60declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 61 62declare <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #2 63 64define arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_m_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 { 65; CHECK-LABEL: test_vmaxaq_m_s16: 66; CHECK: @ %bb.0: @ %entry 67; CHECK-NEXT: vmsr p0, r0 68; CHECK-NEXT: vpst 69; CHECK-NEXT: vmaxat.s16 q0, q1 70; CHECK-NEXT: bx lr 71entry: 72 %0 = zext i16 %p to i32 73 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 74 %2 = tail call <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1) 75 ret <8 x i16> %2 76} 77 78declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 79 80declare <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #2 81 82define arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_m_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 { 83; CHECK-LABEL: test_vmaxaq_m_s32: 84; CHECK: @ %bb.0: @ %entry 85; CHECK-NEXT: vmsr p0, r0 86; CHECK-NEXT: vpst 87; CHECK-NEXT: vmaxat.s32 q0, q1 88; CHECK-NEXT: bx lr 89entry: 90 %0 = zext i16 %p to i32 91 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 92 %2 = tail call <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1) 93 ret <4 x i32> %2 94} 95 96declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 97 98declare <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #2 99