1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s 3 4define arm_aapcs_vfpcc <8 x half> @test_vminnmaq_f16(<8 x half> %a, <8 x half> %b) local_unnamed_addr #0 { 5; CHECK-LABEL: test_vminnmaq_f16: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vminnma.f16 q0, q1 8; CHECK-NEXT: bx lr 9entry: 10 %0 = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %a) 11 %1 = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %b) 12 %2 = tail call <8 x half> @llvm.minnum.v8f16(<8 x half> %0, <8 x half> %1) 13 ret <8 x half> %2 14} 15 16declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1 17 18declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1 19 20define arm_aapcs_vfpcc <4 x float> @test_vminnmaq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 { 21; CHECK-LABEL: test_vminnmaq_f32: 22; CHECK: @ %bb.0: @ %entry 23; CHECK-NEXT: vminnma.f32 q0, q1 24; CHECK-NEXT: bx lr 25entry: 26 %0 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %a) 27 %1 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %b) 28 %2 = tail call <4 x float> @llvm.minnum.v4f32(<4 x float> %0, <4 x float> %1) 29 ret <4 x float> %2 30} 31 32declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1 33 34declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1 35 36define arm_aapcs_vfpcc <8 x half> @test_vminnmaq_m_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #0 { 37; CHECK-LABEL: test_vminnmaq_m_f16: 38; CHECK: @ %bb.0: @ %entry 39; CHECK-NEXT: vmsr p0, r0 40; CHECK-NEXT: vpst 41; CHECK-NEXT: vminnmat.f16 q0, q1 42; CHECK-NEXT: bx lr 43entry: 44 %0 = zext i16 %p to i32 45 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 46 %2 = tail call <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1) 47 ret <8 x half> %2 48} 49 50declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 51 52declare <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2 53 54define arm_aapcs_vfpcc <4 x float> @test_vminnmaq_m_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { 55; CHECK-LABEL: test_vminnmaq_m_f32: 56; CHECK: @ %bb.0: @ %entry 57; CHECK-NEXT: vmsr p0, r0 58; CHECK-NEXT: vpst 59; CHECK-NEXT: vminnmat.f32 q0, q1 60; CHECK-NEXT: bx lr 61entry: 62 %0 = zext i16 %p to i32 63 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 64 %2 = tail call <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x i1> %1) 65 ret <4 x float> %2 66} 67 68declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 69 70declare <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2 71