1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s 3 4define arm_aapcs_vfpcc <8 x half> @test_vminnmq_f16(<8 x half> %a, <8 x half> %b) local_unnamed_addr #0 { 5; CHECK-LABEL: test_vminnmq_f16: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vminnm.f16 q0, q0, q1 8; CHECK-NEXT: bx lr 9entry: 10 %0 = tail call <8 x half> @llvm.minnum.v8f16(<8 x half> %a, <8 x half> %b) 11 ret <8 x half> %0 12} 13 14declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1 15 16define arm_aapcs_vfpcc <4 x float> @test_vminnmq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 { 17; CHECK-LABEL: test_vminnmq_f32: 18; CHECK: @ %bb.0: @ %entry 19; CHECK-NEXT: vminnm.f32 q0, q0, q1 20; CHECK-NEXT: bx lr 21entry: 22 %0 = tail call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b) 23 ret <4 x float> %0 24} 25 26declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1 27 28define arm_aapcs_vfpcc <8 x half> @test_vminnmq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #0 { 29; CHECK-LABEL: test_vminnmq_m_f16: 30; CHECK: @ %bb.0: @ %entry 31; CHECK-NEXT: vmsr p0, r0 32; CHECK-NEXT: vpst 33; CHECK-NEXT: vminnmt.f16 q0, q1, q2 34; CHECK-NEXT: bx lr 35entry: 36 %0 = zext i16 %p to i32 37 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 38 %2 = tail call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, i32 0, <8 x i1> %1, <8 x half> %inactive) 39 ret <8 x half> %2 40} 41 42declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 43 44declare <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2 45 46define arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { 47; CHECK-LABEL: test_vminnmq_m_f32: 48; CHECK: @ %bb.0: @ %entry 49; CHECK-NEXT: vmsr p0, r0 50; CHECK-NEXT: vpst 51; CHECK-NEXT: vminnmt.f32 q0, q1, q2 52; CHECK-NEXT: bx lr 53entry: 54 %0 = zext i16 %p to i32 55 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 56 %2 = tail call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, i32 0, <4 x i1> %1, <4 x float> %inactive) 57 ret <4 x float> %2 58} 59 60declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 61 62declare <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2 63 64define arm_aapcs_vfpcc <8 x half> @test_vminnmq_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #0 { 65; CHECK-LABEL: test_vminnmq_x_f16: 66; CHECK: @ %bb.0: @ %entry 67; CHECK-NEXT: vmsr p0, r0 68; CHECK-NEXT: vpst 69; CHECK-NEXT: vminnmt.f16 q0, q0, q1 70; CHECK-NEXT: bx lr 71entry: 72 %0 = zext i16 %p to i32 73 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 74 %2 = tail call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, i32 0, <8 x i1> %1, <8 x half> undef) 75 ret <8 x half> %2 76} 77 78define arm_aapcs_vfpcc <4 x float> @test_vminnmq_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { 79; CHECK-LABEL: test_vminnmq_x_f32: 80; CHECK: @ %bb.0: @ %entry 81; CHECK-NEXT: vmsr p0, r0 82; CHECK-NEXT: vpst 83; CHECK-NEXT: vminnmt.f32 q0, q0, q1 84; CHECK-NEXT: bx lr 85entry: 86 %0 = zext i16 %p to i32 87 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 88 %2 = tail call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, i32 0, <4 x i1> %1, <4 x float> undef) 89 ret <4 x float> %2 90} 91 92