1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s 3 4define arm_aapcs_vfpcc <16 x i8> @test_vminq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 5; CHECK-LABEL: test_vminq_u8: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vmin.u8 q0, q0, q1 8; CHECK-NEXT: bx lr 9entry: 10 %0 = icmp ugt <16 x i8> %a, %b 11 %1 = select <16 x i1> %0, <16 x i8> %b, <16 x i8> %a 12 ret <16 x i8> %1 13} 14 15define arm_aapcs_vfpcc <8 x i16> @test_vminq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 { 16; CHECK-LABEL: test_vminq_s16: 17; CHECK: @ %bb.0: @ %entry 18; CHECK-NEXT: vmin.s16 q0, q0, q1 19; CHECK-NEXT: bx lr 20entry: 21 %0 = icmp sgt <8 x i16> %a, %b 22 %1 = select <8 x i1> %0, <8 x i16> %b, <8 x i16> %a 23 ret <8 x i16> %1 24} 25 26define arm_aapcs_vfpcc <4 x i32> @test_vminq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 { 27; CHECK-LABEL: test_vminq_u32: 28; CHECK: @ %bb.0: @ %entry 29; CHECK-NEXT: vmin.u32 q0, q0, q1 30; CHECK-NEXT: bx lr 31entry: 32 %0 = icmp ugt <4 x i32> %a, %b 33 %1 = select <4 x i1> %0, <4 x i32> %b, <4 x i32> %a 34 ret <4 x i32> %1 35} 36 37define arm_aapcs_vfpcc <16 x i8> @test_vminq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 { 38; CHECK-LABEL: test_vminq_m_s8: 39; CHECK: @ %bb.0: @ %entry 40; CHECK-NEXT: vmsr p0, r0 41; CHECK-NEXT: vpst 42; CHECK-NEXT: vmint.s8 q0, q1, q2 43; CHECK-NEXT: bx lr 44entry: 45 %0 = zext i16 %p to i32 46 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) 47 %2 = tail call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, <16 x i1> %1, <16 x i8> %inactive) 48 ret <16 x i8> %2 49} 50 51declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 52 53declare <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2 54 55define arm_aapcs_vfpcc <8 x i16> @test_vminq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 { 56; CHECK-LABEL: test_vminq_m_u16: 57; CHECK: @ %bb.0: @ %entry 58; CHECK-NEXT: vmsr p0, r0 59; CHECK-NEXT: vpst 60; CHECK-NEXT: vmint.u16 q0, q1, q2 61; CHECK-NEXT: bx lr 62entry: 63 %0 = zext i16 %p to i32 64 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 65 %2 = tail call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, <8 x i1> %1, <8 x i16> %inactive) 66 ret <8 x i16> %2 67} 68 69declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 70 71declare <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2 72 73define arm_aapcs_vfpcc <4 x i32> @test_vminq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 { 74; CHECK-LABEL: test_vminq_m_s32: 75; CHECK: @ %bb.0: @ %entry 76; CHECK-NEXT: vmsr p0, r0 77; CHECK-NEXT: vpst 78; CHECK-NEXT: vmint.s32 q0, q1, q2 79; CHECK-NEXT: bx lr 80entry: 81 %0 = zext i16 %p to i32 82 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 83 %2 = tail call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, <4 x i1> %1, <4 x i32> %inactive) 84 ret <4 x i32> %2 85} 86 87declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 88 89declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2 90 91define arm_aapcs_vfpcc <16 x i8> @test_vminq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 { 92; CHECK-LABEL: test_vminq_x_u8: 93; CHECK: @ %bb.0: @ %entry 94; CHECK-NEXT: vmsr p0, r0 95; CHECK-NEXT: vpst 96; CHECK-NEXT: vmint.u8 q0, q0, q1 97; CHECK-NEXT: bx lr 98entry: 99 %0 = zext i16 %p to i32 100 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) 101 %2 = tail call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, <16 x i1> %1, <16 x i8> undef) 102 ret <16 x i8> %2 103} 104 105define arm_aapcs_vfpcc <8 x i16> @test_vminq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 { 106; CHECK-LABEL: test_vminq_x_s16: 107; CHECK: @ %bb.0: @ %entry 108; CHECK-NEXT: vmsr p0, r0 109; CHECK-NEXT: vpst 110; CHECK-NEXT: vmint.s16 q0, q0, q1 111; CHECK-NEXT: bx lr 112entry: 113 %0 = zext i16 %p to i32 114 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 115 %2 = tail call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, <8 x i1> %1, <8 x i16> undef) 116 ret <8 x i16> %2 117} 118 119define arm_aapcs_vfpcc <4 x i32> @test_vminq_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 { 120; CHECK-LABEL: test_vminq_x_s32: 121; CHECK: @ %bb.0: @ %entry 122; CHECK-NEXT: vmsr p0, r0 123; CHECK-NEXT: vpst 124; CHECK-NEXT: vmint.s32 q0, q0, q1 125; CHECK-NEXT: bx lr 126entry: 127 %0 = zext i16 %p to i32 128 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 129 %2 = tail call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, <4 x i1> %1, <4 x i32> undef) 130 ret <4 x i32> %2 131} 132 133