1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s 3 4define arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_s16(<16 x i8> %a, <8 x i16> %b) { 5; CHECK-LABEL: test_vqmovnbq_s16: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vqmovnb.s16 q0, q1 8; CHECK-NEXT: bx lr 9entry: 10 %0 = tail call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 0, i32 0, i32 0) 11 ret <16 x i8> %0 12} 13 14define arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_s32(<8 x i16> %a, <4 x i32> %b) { 15; CHECK-LABEL: test_vqmovnbq_s32: 16; CHECK: @ %bb.0: @ %entry 17; CHECK-NEXT: vqmovnb.s32 q0, q1 18; CHECK-NEXT: bx lr 19entry: 20 %0 = tail call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 0, i32 0, i32 0) 21 ret <8 x i16> %0 22} 23 24define arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_u16(<16 x i8> %a, <8 x i16> %b) { 25; CHECK-LABEL: test_vqmovnbq_u16: 26; CHECK: @ %bb.0: @ %entry 27; CHECK-NEXT: vqmovnb.u16 q0, q1 28; CHECK-NEXT: bx lr 29entry: 30 %0 = tail call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 1, i32 1, i32 0) 31 ret <16 x i8> %0 32} 33 34define arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_u32(<8 x i16> %a, <4 x i32> %b) { 35; CHECK-LABEL: test_vqmovnbq_u32: 36; CHECK: @ %bb.0: @ %entry 37; CHECK-NEXT: vqmovnb.u32 q0, q1 38; CHECK-NEXT: bx lr 39entry: 40 %0 = tail call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 1, i32 1, i32 0) 41 ret <8 x i16> %0 42} 43 44define arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_s16(<16 x i8> %a, <8 x i16> %b) { 45; CHECK-LABEL: test_vqmovntq_s16: 46; CHECK: @ %bb.0: @ %entry 47; CHECK-NEXT: vqmovnt.s16 q0, q1 48; CHECK-NEXT: bx lr 49entry: 50 %0 = tail call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 0, i32 0, i32 1) 51 ret <16 x i8> %0 52} 53 54define arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_s32(<8 x i16> %a, <4 x i32> %b) { 55; CHECK-LABEL: test_vqmovntq_s32: 56; CHECK: @ %bb.0: @ %entry 57; CHECK-NEXT: vqmovnt.s32 q0, q1 58; CHECK-NEXT: bx lr 59entry: 60 %0 = tail call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 0, i32 0, i32 1) 61 ret <8 x i16> %0 62} 63 64define arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_u16(<16 x i8> %a, <8 x i16> %b) { 65; CHECK-LABEL: test_vqmovntq_u16: 66; CHECK: @ %bb.0: @ %entry 67; CHECK-NEXT: vqmovnt.u16 q0, q1 68; CHECK-NEXT: bx lr 69entry: 70 %0 = tail call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 1, i32 1, i32 1) 71 ret <16 x i8> %0 72} 73 74define arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_u32(<8 x i16> %a, <4 x i32> %b) { 75; CHECK-LABEL: test_vqmovntq_u32: 76; CHECK: @ %bb.0: @ %entry 77; CHECK-NEXT: vqmovnt.u32 q0, q1 78; CHECK-NEXT: bx lr 79entry: 80 %0 = tail call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 1, i32 1, i32 1) 81 ret <8 x i16> %0 82} 83 84define arm_aapcs_vfpcc <16 x i8> @test_vqmovunbq_s16(<16 x i8> %a, <8 x i16> %b) { 85; CHECK-LABEL: test_vqmovunbq_s16: 86; CHECK: @ %bb.0: @ %entry 87; CHECK-NEXT: vqmovunb.s16 q0, q1 88; CHECK-NEXT: bx lr 89entry: 90 %0 = tail call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 1, i32 0, i32 0) 91 ret <16 x i8> %0 92} 93 94define arm_aapcs_vfpcc <8 x i16> @test_vqmovunbq_s32(<8 x i16> %a, <4 x i32> %b) { 95; CHECK-LABEL: test_vqmovunbq_s32: 96; CHECK: @ %bb.0: @ %entry 97; CHECK-NEXT: vqmovunb.s32 q0, q1 98; CHECK-NEXT: bx lr 99entry: 100 %0 = tail call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 1, i32 0, i32 0) 101 ret <8 x i16> %0 102} 103 104define arm_aapcs_vfpcc <16 x i8> @test_vqmovuntq_s16(<16 x i8> %a, <8 x i16> %b) { 105; CHECK-LABEL: test_vqmovuntq_s16: 106; CHECK: @ %bb.0: @ %entry 107; CHECK-NEXT: vqmovunt.s16 q0, q1 108; CHECK-NEXT: bx lr 109entry: 110 %0 = tail call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 1, i32 0, i32 1) 111 ret <16 x i8> %0 112} 113 114define arm_aapcs_vfpcc <8 x i16> @test_vqmovuntq_s32(<8 x i16> %a, <4 x i32> %b) { 115; CHECK-LABEL: test_vqmovuntq_s32: 116; CHECK: @ %bb.0: @ %entry 117; CHECK-NEXT: vqmovunt.s32 q0, q1 118; CHECK-NEXT: bx lr 119entry: 120 %0 = tail call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 1, i32 0, i32 1) 121 ret <8 x i16> %0 122} 123 124define arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) { 125; CHECK-LABEL: test_vqmovnbq_m_s16: 126; CHECK: @ %bb.0: @ %entry 127; CHECK-NEXT: vmsr p0, r0 128; CHECK-NEXT: vpst 129; CHECK-NEXT: vqmovnbt.s16 q0, q1 130; CHECK-NEXT: bx lr 131entry: 132 %0 = zext i16 %p to i32 133 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 134 %2 = tail call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 0, i32 0, i32 0, <8 x i1> %1) 135 ret <16 x i8> %2 136} 137 138define arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) { 139; CHECK-LABEL: test_vqmovnbq_m_s32: 140; CHECK: @ %bb.0: @ %entry 141; CHECK-NEXT: vmsr p0, r0 142; CHECK-NEXT: vpst 143; CHECK-NEXT: vqmovnbt.s32 q0, q1 144; CHECK-NEXT: bx lr 145entry: 146 %0 = zext i16 %p to i32 147 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 148 %2 = tail call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 0, i32 0, i32 0, <4 x i1> %1) 149 ret <8 x i16> %2 150} 151 152define arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_u16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) { 153; CHECK-LABEL: test_vqmovnbq_m_u16: 154; CHECK: @ %bb.0: @ %entry 155; CHECK-NEXT: vmsr p0, r0 156; CHECK-NEXT: vpst 157; CHECK-NEXT: vqmovnbt.u16 q0, q1 158; CHECK-NEXT: bx lr 159entry: 160 %0 = zext i16 %p to i32 161 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 162 %2 = tail call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 1, i32 1, i32 0, <8 x i1> %1) 163 ret <16 x i8> %2 164} 165 166define arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_u32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) { 167; CHECK-LABEL: test_vqmovnbq_m_u32: 168; CHECK: @ %bb.0: @ %entry 169; CHECK-NEXT: vmsr p0, r0 170; CHECK-NEXT: vpst 171; CHECK-NEXT: vqmovnbt.u32 q0, q1 172; CHECK-NEXT: bx lr 173entry: 174 %0 = zext i16 %p to i32 175 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 176 %2 = tail call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 1, i32 1, i32 0, <4 x i1> %1) 177 ret <8 x i16> %2 178} 179 180define arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_m_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) { 181; CHECK-LABEL: test_vqmovntq_m_s16: 182; CHECK: @ %bb.0: @ %entry 183; CHECK-NEXT: vmsr p0, r0 184; CHECK-NEXT: vpst 185; CHECK-NEXT: vqmovntt.s16 q0, q1 186; CHECK-NEXT: bx lr 187entry: 188 %0 = zext i16 %p to i32 189 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 190 %2 = tail call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 0, i32 0, i32 1, <8 x i1> %1) 191 ret <16 x i8> %2 192} 193 194define arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_m_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) { 195; CHECK-LABEL: test_vqmovntq_m_s32: 196; CHECK: @ %bb.0: @ %entry 197; CHECK-NEXT: vmsr p0, r0 198; CHECK-NEXT: vpst 199; CHECK-NEXT: vqmovntt.s32 q0, q1 200; CHECK-NEXT: bx lr 201entry: 202 %0 = zext i16 %p to i32 203 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 204 %2 = tail call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 0, i32 0, i32 1, <4 x i1> %1) 205 ret <8 x i16> %2 206} 207 208define arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_m_u16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) { 209; CHECK-LABEL: test_vqmovntq_m_u16: 210; CHECK: @ %bb.0: @ %entry 211; CHECK-NEXT: vmsr p0, r0 212; CHECK-NEXT: vpst 213; CHECK-NEXT: vqmovntt.u16 q0, q1 214; CHECK-NEXT: bx lr 215entry: 216 %0 = zext i16 %p to i32 217 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 218 %2 = tail call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 1, i32 1, i32 1, <8 x i1> %1) 219 ret <16 x i8> %2 220} 221 222define arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_m_u32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) { 223; CHECK-LABEL: test_vqmovntq_m_u32: 224; CHECK: @ %bb.0: @ %entry 225; CHECK-NEXT: vmsr p0, r0 226; CHECK-NEXT: vpst 227; CHECK-NEXT: vqmovntt.u32 q0, q1 228; CHECK-NEXT: bx lr 229entry: 230 %0 = zext i16 %p to i32 231 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 232 %2 = tail call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 1, i32 1, i32 1, <4 x i1> %1) 233 ret <8 x i16> %2 234} 235 236define arm_aapcs_vfpcc <16 x i8> @test_vqmovunbq_m_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) { 237; CHECK-LABEL: test_vqmovunbq_m_s16: 238; CHECK: @ %bb.0: @ %entry 239; CHECK-NEXT: vmsr p0, r0 240; CHECK-NEXT: vpst 241; CHECK-NEXT: vqmovunbt.s16 q0, q1 242; CHECK-NEXT: bx lr 243entry: 244 %0 = zext i16 %p to i32 245 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 246 %2 = tail call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 1, i32 0, i32 0, <8 x i1> %1) 247 ret <16 x i8> %2 248} 249 250define arm_aapcs_vfpcc <8 x i16> @test_vqmovunbq_m_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) { 251; CHECK-LABEL: test_vqmovunbq_m_s32: 252; CHECK: @ %bb.0: @ %entry 253; CHECK-NEXT: vmsr p0, r0 254; CHECK-NEXT: vpst 255; CHECK-NEXT: vqmovunbt.s32 q0, q1 256; CHECK-NEXT: bx lr 257entry: 258 %0 = zext i16 %p to i32 259 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 260 %2 = tail call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 1, i32 0, i32 0, <4 x i1> %1) 261 ret <8 x i16> %2 262} 263 264define arm_aapcs_vfpcc <16 x i8> @test_vqmovuntq_m_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) { 265; CHECK-LABEL: test_vqmovuntq_m_s16: 266; CHECK: @ %bb.0: @ %entry 267; CHECK-NEXT: vmsr p0, r0 268; CHECK-NEXT: vpst 269; CHECK-NEXT: vqmovuntt.s16 q0, q1 270; CHECK-NEXT: bx lr 271entry: 272 %0 = zext i16 %p to i32 273 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 274 %2 = tail call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 1, i32 0, i32 1, <8 x i1> %1) 275 ret <16 x i8> %2 276} 277 278define arm_aapcs_vfpcc <8 x i16> @test_vqmovuntq_m_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) { 279; CHECK-LABEL: test_vqmovuntq_m_s32: 280; CHECK: @ %bb.0: @ %entry 281; CHECK-NEXT: vmsr p0, r0 282; CHECK-NEXT: vpst 283; CHECK-NEXT: vqmovuntt.s32 q0, q1 284; CHECK-NEXT: bx lr 285entry: 286 %0 = zext i16 %p to i32 287 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 288 %2 = tail call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 1, i32 0, i32 1, <4 x i1> %1) 289 ret <8 x i16> %2 290} 291 292declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) 293declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) 294 295declare <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32) 296declare <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32) 297 298declare <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, <8 x i1>) 299declare <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, <4 x i1>) 300