1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s 3 4define arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 5; CHECK-LABEL: test_vrmulhq_u8: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vrmulh.u8 q0, q0, q1 8; CHECK-NEXT: bx lr 9entry: 10 %0 = tail call <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1) 11 ret <16 x i8> %0 12} 13 14declare <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1 15 16define arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 { 17; CHECK-LABEL: test_vrmulhq_s16: 18; CHECK: @ %bb.0: @ %entry 19; CHECK-NEXT: vrmulh.s16 q0, q0, q1 20; CHECK-NEXT: bx lr 21entry: 22 %0 = tail call <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0) 23 ret <8 x i16> %0 24} 25 26declare <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1 27 28define arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 { 29; CHECK-LABEL: test_vrmulhq_u32: 30; CHECK: @ %bb.0: @ %entry 31; CHECK-NEXT: vrmulh.u32 q0, q0, q1 32; CHECK-NEXT: bx lr 33entry: 34 %0 = tail call <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1) 35 ret <4 x i32> %0 36} 37 38declare <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1 39 40define arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 { 41; CHECK-LABEL: test_vrmulhq_m_s8: 42; CHECK: @ %bb.0: @ %entry 43; CHECK-NEXT: vmsr p0, r0 44; CHECK-NEXT: vpst 45; CHECK-NEXT: vrmulht.s8 q0, q1, q2 46; CHECK-NEXT: bx lr 47entry: 48 %0 = zext i16 %p to i32 49 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) 50 %2 = tail call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, <16 x i1> %1, <16 x i8> %inactive) 51 ret <16 x i8> %2 52} 53 54declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 55 56declare <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 57 58define arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 { 59; CHECK-LABEL: test_vrmulhq_m_u16: 60; CHECK: @ %bb.0: @ %entry 61; CHECK-NEXT: vmsr p0, r0 62; CHECK-NEXT: vpst 63; CHECK-NEXT: vrmulht.u16 q0, q1, q2 64; CHECK-NEXT: bx lr 65entry: 66 %0 = zext i16 %p to i32 67 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 68 %2 = tail call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, <8 x i1> %1, <8 x i16> %inactive) 69 ret <8 x i16> %2 70} 71 72declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 73 74declare <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 75 76define arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 { 77; CHECK-LABEL: test_vrmulhq_m_s32: 78; CHECK: @ %bb.0: @ %entry 79; CHECK-NEXT: vmsr p0, r0 80; CHECK-NEXT: vpst 81; CHECK-NEXT: vrmulht.s32 q0, q1, q2 82; CHECK-NEXT: bx lr 83entry: 84 %0 = zext i16 %p to i32 85 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 86 %2 = tail call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, <4 x i1> %1, <4 x i32> %inactive) 87 ret <4 x i32> %2 88} 89 90declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 91 92declare <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 93 94define arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 { 95; CHECK-LABEL: test_vrmulhq_x_u8: 96; CHECK: @ %bb.0: @ %entry 97; CHECK-NEXT: vmsr p0, r0 98; CHECK-NEXT: vpst 99; CHECK-NEXT: vrmulht.u8 q0, q0, q1 100; CHECK-NEXT: bx lr 101entry: 102 %0 = zext i16 %p to i32 103 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) 104 %2 = tail call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, <16 x i1> %1, <16 x i8> undef) 105 ret <16 x i8> %2 106} 107 108define arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 { 109; CHECK-LABEL: test_vrmulhq_x_s16: 110; CHECK: @ %bb.0: @ %entry 111; CHECK-NEXT: vmsr p0, r0 112; CHECK-NEXT: vpst 113; CHECK-NEXT: vrmulht.s16 q0, q0, q1 114; CHECK-NEXT: bx lr 115entry: 116 %0 = zext i16 %p to i32 117 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 118 %2 = tail call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, <8 x i1> %1, <8 x i16> undef) 119 ret <8 x i16> %2 120} 121 122define arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 { 123; CHECK-LABEL: test_vrmulhq_m_u32: 124; CHECK: @ %bb.0: @ %entry 125; CHECK-NEXT: vmsr p0, r0 126; CHECK-NEXT: vpst 127; CHECK-NEXT: vrmulht.u32 q0, q0, q1 128; CHECK-NEXT: bx lr 129entry: 130 %0 = zext i16 %p to i32 131 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 132 %2 = tail call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, <4 x i1> %1, <4 x i32> undef) 133 ret <4 x i32> %2 134} 135 136