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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
3
4define arm_aapcs_vfpcc i32 @build_v2i_v4i1_1() {
5; CHECK-LABEL: build_v2i_v4i1_1:
6; CHECK:       @ %bb.0:
7; CHECK-NEXT:    movw r0, #65535
8; CHECK-NEXT:    bx lr
9  %r = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 1, i1 1, i1 1, i1 1>)
10  ret i32 %r
11}
12define arm_aapcs_vfpcc i32 @build_v2i_v4i1_0() {
13; CHECK-LABEL: build_v2i_v4i1_0:
14; CHECK:       @ %bb.0:
15; CHECK-NEXT:    movs r0, #0
16; CHECK-NEXT:    bx lr
17  %r = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 0, i1 0, i1 0>)
18  ret i32 %r
19}
20define arm_aapcs_vfpcc i32 @build_v2i_v4i1_5() {
21; CHECK-LABEL: build_v2i_v4i1_5:
22; CHECK:       @ %bb.0:
23; CHECK-NEXT:    movw r0, #61680
24; CHECK-NEXT:    bx lr
25  %r = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 1, i1 0, i1 1>)
26  ret i32 %r
27}
28
29define arm_aapcs_vfpcc i32 @build_v2i_v8i1_1() {
30; CHECK-LABEL: build_v2i_v8i1_1:
31; CHECK:       @ %bb.0:
32; CHECK-NEXT:    movw r0, #65535
33; CHECK-NEXT:    bx lr
34  %r = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>)
35  ret i32 %r
36}
37define arm_aapcs_vfpcc i32 @build_v2i_v8i1_0() {
38; CHECK-LABEL: build_v2i_v8i1_0:
39; CHECK:       @ %bb.0:
40; CHECK-NEXT:    movs r0, #0
41; CHECK-NEXT:    bx lr
42  %r = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>)
43  ret i32 %r
44}
45define arm_aapcs_vfpcc i32 @build_v2i_v8i1_5() {
46; CHECK-LABEL: build_v2i_v8i1_5:
47; CHECK:       @ %bb.0:
48; CHECK-NEXT:    movw r0, #52428
49; CHECK-NEXT:    bx lr
50  %r = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
51  ret i32 %r
52}
53
54define arm_aapcs_vfpcc i32 @build_v2i_v16i1_1() {
55; CHECK-LABEL: build_v2i_v16i1_1:
56; CHECK:       @ %bb.0:
57; CHECK-NEXT:    movw r0, #65535
58; CHECK-NEXT:    bx lr
59  %r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>)
60  ret i32 %r
61}
62define arm_aapcs_vfpcc i32 @build_v2i_v16i1_0() {
63; CHECK-LABEL: build_v2i_v16i1_0:
64; CHECK:       @ %bb.0:
65; CHECK-NEXT:    movs r0, #0
66; CHECK-NEXT:    bx lr
67  %r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>)
68  ret i32 %r
69}
70define arm_aapcs_vfpcc i32 @build_v2i_v16i1_5() {
71; CHECK-LABEL: build_v2i_v16i1_5:
72; CHECK:       @ %bb.0:
73; CHECK-NEXT:    movw r0, #43690
74; CHECK-NEXT:    bx lr
75  %r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
76  ret i32 %r
77}
78
79
80
81define arm_aapcs_vfpcc <4 x i32> @build_i2v_v4i1_1() {
82; CHECK-LABEL: build_i2v_v4i1_1:
83; CHECK:       @ %bb.0:
84; CHECK-NEXT:    movw r0, #65535
85; CHECK-NEXT:    vmov.i32 q0, #0x0
86; CHECK-NEXT:    vmsr p0, r0
87; CHECK-NEXT:    vmov.i8 q1, #0xff
88; CHECK-NEXT:    vpsel q0, q1, q0
89; CHECK-NEXT:    bx lr
90  %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 65535)
91  %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
92  ret <4 x i32> %r
93}
94define arm_aapcs_vfpcc <4 x i32> @build_i2v_v4i1_0() {
95; CHECK-LABEL: build_i2v_v4i1_0:
96; CHECK:       @ %bb.0:
97; CHECK-NEXT:    movs r0, #0
98; CHECK-NEXT:    vmov.i32 q0, #0x0
99; CHECK-NEXT:    vmsr p0, r0
100; CHECK-NEXT:    vmov.i8 q1, #0xff
101; CHECK-NEXT:    vpsel q0, q1, q0
102; CHECK-NEXT:    bx lr
103  %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 0)
104  %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
105  ret <4 x i32> %r
106}
107define arm_aapcs_vfpcc <4 x i32> @build_i2v_v4i1_5() {
108; CHECK-LABEL: build_i2v_v4i1_5:
109; CHECK:       @ %bb.0:
110; CHECK-NEXT:    movw r0, #61680
111; CHECK-NEXT:    vmov.i32 q0, #0x0
112; CHECK-NEXT:    vmsr p0, r0
113; CHECK-NEXT:    vmov.i8 q1, #0xff
114; CHECK-NEXT:    vpsel q0, q1, q0
115; CHECK-NEXT:    bx lr
116  %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 61680)
117  %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
118  ret <4 x i32> %r
119}
120
121define arm_aapcs_vfpcc <8 x i16> @build_i2v_v8i1_1() {
122; CHECK-LABEL: build_i2v_v8i1_1:
123; CHECK:       @ %bb.0:
124; CHECK-NEXT:    movw r0, #65535
125; CHECK-NEXT:    vmov.i32 q0, #0x0
126; CHECK-NEXT:    vmsr p0, r0
127; CHECK-NEXT:    vmov.i8 q1, #0xff
128; CHECK-NEXT:    vpsel q0, q1, q0
129; CHECK-NEXT:    bx lr
130  %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 65535)
131  %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
132  ret <8 x i16> %r
133}
134define arm_aapcs_vfpcc <8 x i16> @build_i2v_v8i1_0() {
135; CHECK-LABEL: build_i2v_v8i1_0:
136; CHECK:       @ %bb.0:
137; CHECK-NEXT:    movs r0, #0
138; CHECK-NEXT:    vmov.i32 q0, #0x0
139; CHECK-NEXT:    vmsr p0, r0
140; CHECK-NEXT:    vmov.i8 q1, #0xff
141; CHECK-NEXT:    vpsel q0, q1, q0
142; CHECK-NEXT:    bx lr
143  %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 0)
144  %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
145  ret <8 x i16> %r
146}
147define arm_aapcs_vfpcc <8 x i16> @build_i2v_v8i1_5() {
148; CHECK-LABEL: build_i2v_v8i1_5:
149; CHECK:       @ %bb.0:
150; CHECK-NEXT:    movw r0, #52428
151; CHECK-NEXT:    vmov.i32 q0, #0x0
152; CHECK-NEXT:    vmsr p0, r0
153; CHECK-NEXT:    vmov.i8 q1, #0xff
154; CHECK-NEXT:    vpsel q0, q1, q0
155; CHECK-NEXT:    bx lr
156  %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 52428)
157  %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
158  ret <8 x i16> %r
159}
160
161define arm_aapcs_vfpcc <16 x i8> @build_i2v_v16i1_1() {
162; CHECK-LABEL: build_i2v_v16i1_1:
163; CHECK:       @ %bb.0:
164; CHECK-NEXT:    movw r0, #65535
165; CHECK-NEXT:    vmov.i32 q0, #0x0
166; CHECK-NEXT:    vmsr p0, r0
167; CHECK-NEXT:    vmov.i8 q1, #0xff
168; CHECK-NEXT:    vpsel q0, q1, q0
169; CHECK-NEXT:    bx lr
170  %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 65535)
171  %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
172  ret <16 x i8> %r
173}
174define arm_aapcs_vfpcc <16 x i8> @build_i2v_v16i1_0() {
175; CHECK-LABEL: build_i2v_v16i1_0:
176; CHECK:       @ %bb.0:
177; CHECK-NEXT:    movs r0, #0
178; CHECK-NEXT:    vmov.i32 q0, #0x0
179; CHECK-NEXT:    vmsr p0, r0
180; CHECK-NEXT:    vmov.i8 q1, #0xff
181; CHECK-NEXT:    vpsel q0, q1, q0
182; CHECK-NEXT:    bx lr
183  %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 0)
184  %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
185  ret <16 x i8> %r
186}
187define arm_aapcs_vfpcc <16 x i8> @build_i2v_v16i1_5() {
188; CHECK-LABEL: build_i2v_v16i1_5:
189; CHECK:       @ %bb.0:
190; CHECK-NEXT:    movw r0, #43690
191; CHECK-NEXT:    vmov.i32 q0, #0x0
192; CHECK-NEXT:    vmsr p0, r0
193; CHECK-NEXT:    vmov.i8 q1, #0xff
194; CHECK-NEXT:    vpsel q0, q1, q0
195; CHECK-NEXT:    bx lr
196  %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 43690)
197  %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
198  ret <16 x i8> %r
199}
200
201
202define arm_aapcs_vfpcc i32 @build_i2v2i_v4i1_5() {
203; CHECK-LABEL: build_i2v2i_v4i1_5:
204; CHECK:       @ %bb.0:
205; CHECK-NEXT:    movw r0, #61680
206; CHECK-NEXT:    bx lr
207  %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 61680)
208  %r = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %c)
209  ret i32 %r
210}
211define arm_aapcs_vfpcc i32 @build_i2v2i_v8i1_5() {
212; CHECK-LABEL: build_i2v2i_v8i1_5:
213; CHECK:       @ %bb.0:
214; CHECK-NEXT:    movw r0, #52428
215; CHECK-NEXT:    bx lr
216  %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 52428)
217  %r = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %c)
218  ret i32 %r
219}
220define arm_aapcs_vfpcc i32 @build_i2v2i_v16i1_5() {
221; CHECK-LABEL: build_i2v2i_v16i1_5:
222; CHECK:       @ %bb.0:
223; CHECK-NEXT:    movw r0, #43690
224; CHECK-NEXT:    bx lr
225  %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 43690)
226  %r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %c)
227  ret i32 %r
228}
229
230
231define arm_aapcs_vfpcc <4 x i32> @build_v2i2v_v4i1_v4i1_5() {
232; CHECK-LABEL: build_v2i2v_v4i1_v4i1_5:
233; CHECK:       @ %bb.0:
234; CHECK-NEXT:    movw r0, #61680
235; CHECK-NEXT:    vmov.i32 q0, #0x0
236; CHECK-NEXT:    vmsr p0, r0
237; CHECK-NEXT:    vmov.i8 q1, #0xff
238; CHECK-NEXT:    vpsel q0, q1, q0
239; CHECK-NEXT:    bx lr
240  %b = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 1, i1 0, i1 1>)
241  %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %b)
242  %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
243  ret <4 x i32> %r
244}
245define arm_aapcs_vfpcc <4 x i32> @build_v2i2v_v8i1_v4i1_5() {
246; CHECK-LABEL: build_v2i2v_v8i1_v4i1_5:
247; CHECK:       @ %bb.0:
248; CHECK-NEXT:    movw r0, #52428
249; CHECK-NEXT:    vmov.i32 q0, #0x0
250; CHECK-NEXT:    vmsr p0, r0
251; CHECK-NEXT:    vmov.i8 q1, #0xff
252; CHECK-NEXT:    vpsel q0, q1, q0
253; CHECK-NEXT:    bx lr
254  %b = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
255  %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %b)
256  %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
257  ret <4 x i32> %r
258}
259define arm_aapcs_vfpcc <4 x i32> @build_v2i2v_v16i1_v4i1_5() {
260; CHECK-LABEL: build_v2i2v_v16i1_v4i1_5:
261; CHECK:       @ %bb.0:
262; CHECK-NEXT:    movw r0, #43690
263; CHECK-NEXT:    vmov.i32 q0, #0x0
264; CHECK-NEXT:    vmsr p0, r0
265; CHECK-NEXT:    vmov.i8 q1, #0xff
266; CHECK-NEXT:    vpsel q0, q1, q0
267; CHECK-NEXT:    bx lr
268  %b = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
269  %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %b)
270  %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
271  ret <4 x i32> %r
272}
273
274define arm_aapcs_vfpcc <8 x i16> @build_v2i2v_v4i1_v8i1_5() {
275; CHECK-LABEL: build_v2i2v_v4i1_v8i1_5:
276; CHECK:       @ %bb.0:
277; CHECK-NEXT:    movw r0, #61680
278; CHECK-NEXT:    vmov.i32 q0, #0x0
279; CHECK-NEXT:    vmsr p0, r0
280; CHECK-NEXT:    vmov.i8 q1, #0xff
281; CHECK-NEXT:    vpsel q0, q1, q0
282; CHECK-NEXT:    bx lr
283  %b = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 1, i1 0, i1 1>)
284  %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %b)
285  %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
286  ret <8 x i16> %r
287}
288define arm_aapcs_vfpcc <8 x i16> @build_v2i2v_v8i1_v8i1_5() {
289; CHECK-LABEL: build_v2i2v_v8i1_v8i1_5:
290; CHECK:       @ %bb.0:
291; CHECK-NEXT:    movw r0, #52428
292; CHECK-NEXT:    vmov.i32 q0, #0x0
293; CHECK-NEXT:    vmsr p0, r0
294; CHECK-NEXT:    vmov.i8 q1, #0xff
295; CHECK-NEXT:    vpsel q0, q1, q0
296; CHECK-NEXT:    bx lr
297  %b = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
298  %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %b)
299  %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
300  ret <8 x i16> %r
301}
302define arm_aapcs_vfpcc <8 x i16> @build_v2i2v_v16i1_v8i1_5() {
303; CHECK-LABEL: build_v2i2v_v16i1_v8i1_5:
304; CHECK:       @ %bb.0:
305; CHECK-NEXT:    movw r0, #43690
306; CHECK-NEXT:    vmov.i32 q0, #0x0
307; CHECK-NEXT:    vmsr p0, r0
308; CHECK-NEXT:    vmov.i8 q1, #0xff
309; CHECK-NEXT:    vpsel q0, q1, q0
310; CHECK-NEXT:    bx lr
311  %b = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
312  %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %b)
313  %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
314  ret <8 x i16> %r
315}
316
317define arm_aapcs_vfpcc <16 x i8> @build_v2i2v_v4i1_v16i1_5() {
318; CHECK-LABEL: build_v2i2v_v4i1_v16i1_5:
319; CHECK:       @ %bb.0:
320; CHECK-NEXT:    movw r0, #61680
321; CHECK-NEXT:    vmov.i32 q0, #0x0
322; CHECK-NEXT:    vmsr p0, r0
323; CHECK-NEXT:    vmov.i8 q1, #0xff
324; CHECK-NEXT:    vpsel q0, q1, q0
325; CHECK-NEXT:    bx lr
326  %b = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 1, i1 0, i1 1>)
327  %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %b)
328  %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
329  ret <16 x i8> %r
330}
331define arm_aapcs_vfpcc <16 x i8> @build_v2i2v_v8i1_v16i1_5() {
332; CHECK-LABEL: build_v2i2v_v8i1_v16i1_5:
333; CHECK:       @ %bb.0:
334; CHECK-NEXT:    movw r0, #52428
335; CHECK-NEXT:    vmov.i32 q0, #0x0
336; CHECK-NEXT:    vmsr p0, r0
337; CHECK-NEXT:    vmov.i8 q1, #0xff
338; CHECK-NEXT:    vpsel q0, q1, q0
339; CHECK-NEXT:    bx lr
340  %b = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
341  %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %b)
342  %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
343  ret <16 x i8> %r
344}
345define arm_aapcs_vfpcc <16 x i8> @build_v2i2v_v16i1_v16i1_5() {
346; CHECK-LABEL: build_v2i2v_v16i1_v16i1_5:
347; CHECK:       @ %bb.0:
348; CHECK-NEXT:    movw r0, #43690
349; CHECK-NEXT:    vmov.i32 q0, #0x0
350; CHECK-NEXT:    vmsr p0, r0
351; CHECK-NEXT:    vmov.i8 q1, #0xff
352; CHECK-NEXT:    vpsel q0, q1, q0
353; CHECK-NEXT:    bx lr
354  %b = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
355  %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %b)
356  %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
357  ret <16 x i8> %r
358}
359
360declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>)
361declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>)
362declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>)
363
364declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
365declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
366declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
367