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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
3
4define arm_aapcs_vfpcc <4 x i32> @sext_v4i32_v4i32_v4i1(<4 x i32> %m) {
5; CHECK-LABEL: sext_v4i32_v4i32_v4i1:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    vshl.i32 q0, q0, #31
8; CHECK-NEXT:    vshr.s32 q0, q0, #31
9; CHECK-NEXT:    bx lr
10entry:
11  %shl = shl <4 x i32> %m, <i32 31, i32 31, i32 31, i32 31>
12  %shr = ashr exact <4 x i32> %shl, <i32 31, i32 31, i32 31, i32 31>
13  ret <4 x i32> %shr
14}
15
16define arm_aapcs_vfpcc <4 x i32> @sext_v4i32_v4i32_v4i8(<4 x i32> %m) {
17; CHECK-LABEL: sext_v4i32_v4i32_v4i8:
18; CHECK:       @ %bb.0: @ %entry
19; CHECK-NEXT:    vmovlb.s8 q0, q0
20; CHECK-NEXT:    vmovlb.s16 q0, q0
21; CHECK-NEXT:    bx lr
22entry:
23  %shl = shl <4 x i32> %m, <i32 24, i32 24, i32 24, i32 24>
24  %shr = ashr exact <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
25  ret <4 x i32> %shr
26}
27
28define arm_aapcs_vfpcc <4 x i32> @sext_v4i32_v4i32_v4i16(<4 x i32> %m) {
29; CHECK-LABEL: sext_v4i32_v4i32_v4i16:
30; CHECK:       @ %bb.0: @ %entry
31; CHECK-NEXT:    vmovlb.s16 q0, q0
32; CHECK-NEXT:    bx lr
33entry:
34  %shl = shl <4 x i32> %m, <i32 16, i32 16, i32 16, i32 16>
35  %shr = ashr exact <4 x i32> %shl, <i32 16, i32 16, i32 16, i32 16>
36  ret <4 x i32> %shr
37}
38
39define arm_aapcs_vfpcc <8 x i16> @sext_v8i16_v8i16_v8i8(<8 x i16> %m) {
40; CHECK-LABEL: sext_v8i16_v8i16_v8i8:
41; CHECK:       @ %bb.0: @ %entry
42; CHECK-NEXT:    vmovlb.s8 q0, q0
43; CHECK-NEXT:    bx lr
44entry:
45  %shl = shl <8 x i16> %m, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
46  %shr = ashr exact <8 x i16> %shl, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
47  ret <8 x i16> %shr
48}
49
50define arm_aapcs_vfpcc <8 x i16> @sext_v8i16_v8i16_v8i1(<8 x i16> %m) {
51; CHECK-LABEL: sext_v8i16_v8i16_v8i1:
52; CHECK:       @ %bb.0: @ %entry
53; CHECK-NEXT:    vshl.i16 q0, q0, #15
54; CHECK-NEXT:    vshr.s16 q0, q0, #15
55; CHECK-NEXT:    bx lr
56entry:
57  %shl = shl <8 x i16> %m, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
58  %shr = ashr exact <8 x i16> %shl, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
59  ret <8 x i16> %shr
60}
61
62define arm_aapcs_vfpcc <2 x i64> @sext_v2i64_v2i64_v2i32(<2 x i64> %m) {
63; CHECK-LABEL: sext_v2i64_v2i64_v2i32:
64; CHECK:       @ %bb.0: @ %entry
65; CHECK-NEXT:    vmov r0, s0
66; CHECK-NEXT:    vmov.32 q1[0], r0
67; CHECK-NEXT:    asrs r0, r0, #31
68; CHECK-NEXT:    vmov.32 q1[1], r0
69; CHECK-NEXT:    vmov r0, s2
70; CHECK-NEXT:    vmov.32 q1[2], r0
71; CHECK-NEXT:    asrs r0, r0, #31
72; CHECK-NEXT:    vmov.32 q1[3], r0
73; CHECK-NEXT:    vmov q0, q1
74; CHECK-NEXT:    bx lr
75entry:
76  %shl = shl <2 x i64> %m, <i64 32, i64 32>
77  %shr = ashr exact <2 x i64> %shl, <i64 32, i64 32>
78  ret <2 x i64> %shr
79}
80
81define arm_aapcs_vfpcc <2 x i64> @sext_v2i64_v2i64_v2i35(<2 x i64> %m) {
82; CHECK-LABEL: sext_v2i64_v2i64_v2i35:
83; CHECK:       @ %bb.0: @ %entry
84; CHECK-NEXT:    vmov r0, s0
85; CHECK-NEXT:    vmov.32 q1[0], r0
86; CHECK-NEXT:    vmov r0, s1
87; CHECK-NEXT:    sbfx r0, r0, #0, #3
88; CHECK-NEXT:    vmov.32 q1[1], r0
89; CHECK-NEXT:    vmov r0, s2
90; CHECK-NEXT:    vmov.32 q1[2], r0
91; CHECK-NEXT:    vmov r0, s3
92; CHECK-NEXT:    sbfx r0, r0, #0, #3
93; CHECK-NEXT:    vmov.32 q1[3], r0
94; CHECK-NEXT:    vmov q0, q1
95; CHECK-NEXT:    bx lr
96entry:
97  %shl = shl <2 x i64> %m, <i64 29, i64 29>
98  %shr = ashr exact <2 x i64> %shl, <i64 29, i64 29>
99  ret <2 x i64> %shr
100}
101
102define arm_aapcs_vfpcc <8 x i16> @sext_v8i8_v8i16(<8 x i8> %src) {
103; CHECK-LABEL: sext_v8i8_v8i16:
104; CHECK:       @ %bb.0: @ %entry
105; CHECK-NEXT:    vmovlb.s8 q0, q0
106; CHECK-NEXT:    bx lr
107entry:
108  %0 = sext <8 x i8> %src to <8 x i16>
109  ret <8 x i16> %0
110}
111
112define arm_aapcs_vfpcc <4 x i32> @sext_v4i16_v4i32(<4 x i16> %src) {
113; CHECK-LABEL: sext_v4i16_v4i32:
114; CHECK:       @ %bb.0: @ %entry
115; CHECK-NEXT:    vmovlb.s16 q0, q0
116; CHECK-NEXT:    bx lr
117entry:
118  %0 = sext <4 x i16> %src to <4 x i32>
119  ret <4 x i32> %0
120}
121
122define arm_aapcs_vfpcc <4 x i32> @sext_v4i8_v4i32(<4 x i8> %src) {
123; CHECK-LABEL: sext_v4i8_v4i32:
124; CHECK:       @ %bb.0: @ %entry
125; CHECK-NEXT:    vmovlb.s8 q0, q0
126; CHECK-NEXT:    vmovlb.s16 q0, q0
127; CHECK-NEXT:    bx lr
128entry:
129  %0 = sext <4 x i8> %src to <4 x i32>
130  ret <4 x i32> %0
131}
132
133define arm_aapcs_vfpcc <16 x i16> @sext_v16i8_v16i16(<16 x i8> %src) {
134; CHECK-LABEL: sext_v16i8_v16i16:
135; CHECK:       @ %bb.0: @ %entry
136; CHECK-NEXT:    vmov.u8 r0, q0[0]
137; CHECK-NEXT:    vmov.16 q1[0], r0
138; CHECK-NEXT:    vmov.u8 r0, q0[1]
139; CHECK-NEXT:    vmov.16 q1[1], r0
140; CHECK-NEXT:    vmov.u8 r0, q0[2]
141; CHECK-NEXT:    vmov.16 q1[2], r0
142; CHECK-NEXT:    vmov.u8 r0, q0[3]
143; CHECK-NEXT:    vmov.16 q1[3], r0
144; CHECK-NEXT:    vmov.u8 r0, q0[4]
145; CHECK-NEXT:    vmov.16 q1[4], r0
146; CHECK-NEXT:    vmov.u8 r0, q0[5]
147; CHECK-NEXT:    vmov.16 q1[5], r0
148; CHECK-NEXT:    vmov.u8 r0, q0[6]
149; CHECK-NEXT:    vmov.16 q1[6], r0
150; CHECK-NEXT:    vmov.u8 r0, q0[7]
151; CHECK-NEXT:    vmov.16 q1[7], r0
152; CHECK-NEXT:    vmov.u8 r0, q0[8]
153; CHECK-NEXT:    vmovlb.s8 q2, q1
154; CHECK-NEXT:    vmov.16 q1[0], r0
155; CHECK-NEXT:    vmov.u8 r0, q0[9]
156; CHECK-NEXT:    vmov.16 q1[1], r0
157; CHECK-NEXT:    vmov.u8 r0, q0[10]
158; CHECK-NEXT:    vmov.16 q1[2], r0
159; CHECK-NEXT:    vmov.u8 r0, q0[11]
160; CHECK-NEXT:    vmov.16 q1[3], r0
161; CHECK-NEXT:    vmov.u8 r0, q0[12]
162; CHECK-NEXT:    vmov.16 q1[4], r0
163; CHECK-NEXT:    vmov.u8 r0, q0[13]
164; CHECK-NEXT:    vmov.16 q1[5], r0
165; CHECK-NEXT:    vmov.u8 r0, q0[14]
166; CHECK-NEXT:    vmov.16 q1[6], r0
167; CHECK-NEXT:    vmov.u8 r0, q0[15]
168; CHECK-NEXT:    vmov.16 q1[7], r0
169; CHECK-NEXT:    vmov q0, q2
170; CHECK-NEXT:    vmovlb.s8 q1, q1
171; CHECK-NEXT:    bx lr
172entry:
173  %0 = sext <16 x i8> %src to <16 x i16>
174  ret <16 x i16> %0
175}
176
177define arm_aapcs_vfpcc <8 x i32> @sext_v8i16_v8i32(<8 x i16> %src) {
178; CHECK-LABEL: sext_v8i16_v8i32:
179; CHECK:       @ %bb.0: @ %entry
180; CHECK-NEXT:    vmov.u16 r0, q0[0]
181; CHECK-NEXT:    vmov.32 q1[0], r0
182; CHECK-NEXT:    vmov.u16 r0, q0[1]
183; CHECK-NEXT:    vmov.32 q1[1], r0
184; CHECK-NEXT:    vmov.u16 r0, q0[2]
185; CHECK-NEXT:    vmov.32 q1[2], r0
186; CHECK-NEXT:    vmov.u16 r0, q0[3]
187; CHECK-NEXT:    vmov.32 q1[3], r0
188; CHECK-NEXT:    vmov.u16 r0, q0[4]
189; CHECK-NEXT:    vmovlb.s16 q2, q1
190; CHECK-NEXT:    vmov.32 q1[0], r0
191; CHECK-NEXT:    vmov.u16 r0, q0[5]
192; CHECK-NEXT:    vmov.32 q1[1], r0
193; CHECK-NEXT:    vmov.u16 r0, q0[6]
194; CHECK-NEXT:    vmov.32 q1[2], r0
195; CHECK-NEXT:    vmov.u16 r0, q0[7]
196; CHECK-NEXT:    vmov.32 q1[3], r0
197; CHECK-NEXT:    vmov q0, q2
198; CHECK-NEXT:    vmovlb.s16 q1, q1
199; CHECK-NEXT:    bx lr
200entry:
201  %0 = sext <8 x i16> %src to <8 x i32>
202  ret <8 x i32> %0
203}
204
205define arm_aapcs_vfpcc <16 x i32> @sext_v16i8_v16i32(<16 x i8> %src) {
206; CHECK-LABEL: sext_v16i8_v16i32:
207; CHECK:       @ %bb.0: @ %entry
208; CHECK-NEXT:    .vsave {d8, d9}
209; CHECK-NEXT:    vpush {d8, d9}
210; CHECK-NEXT:    vmov.u8 r0, q0[0]
211; CHECK-NEXT:    vmov.32 q1[0], r0
212; CHECK-NEXT:    vmov.u8 r0, q0[1]
213; CHECK-NEXT:    vmov.32 q1[1], r0
214; CHECK-NEXT:    vmov.u8 r0, q0[2]
215; CHECK-NEXT:    vmov.32 q1[2], r0
216; CHECK-NEXT:    vmov.u8 r0, q0[3]
217; CHECK-NEXT:    vmov.32 q1[3], r0
218; CHECK-NEXT:    vmov.u8 r0, q0[4]
219; CHECK-NEXT:    vmovlb.s8 q1, q1
220; CHECK-NEXT:    vmovlb.s16 q4, q1
221; CHECK-NEXT:    vmov.32 q1[0], r0
222; CHECK-NEXT:    vmov.u8 r0, q0[5]
223; CHECK-NEXT:    vmov.32 q1[1], r0
224; CHECK-NEXT:    vmov.u8 r0, q0[6]
225; CHECK-NEXT:    vmov.32 q1[2], r0
226; CHECK-NEXT:    vmov.u8 r0, q0[7]
227; CHECK-NEXT:    vmov.32 q1[3], r0
228; CHECK-NEXT:    vmov.u8 r0, q0[8]
229; CHECK-NEXT:    vmov.32 q2[0], r0
230; CHECK-NEXT:    vmov.u8 r0, q0[9]
231; CHECK-NEXT:    vmov.32 q2[1], r0
232; CHECK-NEXT:    vmov.u8 r0, q0[10]
233; CHECK-NEXT:    vmov.32 q2[2], r0
234; CHECK-NEXT:    vmov.u8 r0, q0[11]
235; CHECK-NEXT:    vmov.32 q2[3], r0
236; CHECK-NEXT:    vmov.u8 r0, q0[12]
237; CHECK-NEXT:    vmov.32 q3[0], r0
238; CHECK-NEXT:    vmov.u8 r0, q0[13]
239; CHECK-NEXT:    vmov.32 q3[1], r0
240; CHECK-NEXT:    vmov.u8 r0, q0[14]
241; CHECK-NEXT:    vmov.32 q3[2], r0
242; CHECK-NEXT:    vmov.u8 r0, q0[15]
243; CHECK-NEXT:    vmov.32 q3[3], r0
244; CHECK-NEXT:    vmovlb.s8 q1, q1
245; CHECK-NEXT:    vmovlb.s8 q2, q2
246; CHECK-NEXT:    vmovlb.s8 q0, q3
247; CHECK-NEXT:    vmovlb.s16 q3, q0
248; CHECK-NEXT:    vmovlb.s16 q1, q1
249; CHECK-NEXT:    vmovlb.s16 q2, q2
250; CHECK-NEXT:    vmov q0, q4
251; CHECK-NEXT:    vpop {d8, d9}
252; CHECK-NEXT:    bx lr
253entry:
254  %0 = sext <16 x i8> %src to <16 x i32>
255  ret <16 x i32> %0
256}
257
258define arm_aapcs_vfpcc <2 x i64> @sext_v2i32_v2i64(<2 x i32> %src) {
259; CHECK-LABEL: sext_v2i32_v2i64:
260; CHECK:       @ %bb.0: @ %entry
261; CHECK-NEXT:    vmov r0, s0
262; CHECK-NEXT:    vmov.32 q1[0], r0
263; CHECK-NEXT:    asrs r0, r0, #31
264; CHECK-NEXT:    vmov.32 q1[1], r0
265; CHECK-NEXT:    vmov r0, s2
266; CHECK-NEXT:    vmov.32 q1[2], r0
267; CHECK-NEXT:    asrs r0, r0, #31
268; CHECK-NEXT:    vmov.32 q1[3], r0
269; CHECK-NEXT:    vmov q0, q1
270; CHECK-NEXT:    bx lr
271entry:
272  %0 = sext <2 x i32> %src to <2 x i64>
273  ret <2 x i64> %0
274}
275
276
277define arm_aapcs_vfpcc <8 x i16> @zext_v8i8_v8i16(<8 x i8> %src) {
278; CHECK-LABEL: zext_v8i8_v8i16:
279; CHECK:       @ %bb.0: @ %entry
280; CHECK-NEXT:    vmovlb.u8 q0, q0
281; CHECK-NEXT:    bx lr
282entry:
283  %0 = zext <8 x i8> %src to <8 x i16>
284  ret <8 x i16> %0
285}
286
287define arm_aapcs_vfpcc <4 x i32> @zext_v4i16_v4i32(<4 x i16> %src) {
288; CHECK-LABEL: zext_v4i16_v4i32:
289; CHECK:       @ %bb.0: @ %entry
290; CHECK-NEXT:    vmovlb.u16 q0, q0
291; CHECK-NEXT:    bx lr
292entry:
293  %0 = zext <4 x i16> %src to <4 x i32>
294  ret <4 x i32> %0
295}
296
297define arm_aapcs_vfpcc <4 x i32> @zext_v4i8_v4i32(<4 x i8> %src) {
298; CHECK-LABEL: zext_v4i8_v4i32:
299; CHECK:       @ %bb.0: @ %entry
300; CHECK-NEXT:    vmov.i32 q1, #0xff
301; CHECK-NEXT:    vand q0, q0, q1
302; CHECK-NEXT:    bx lr
303entry:
304  %0 = zext <4 x i8> %src to <4 x i32>
305  ret <4 x i32> %0
306}
307
308define arm_aapcs_vfpcc <16 x i16> @zext_v16i8_v16i16(<16 x i8> %src) {
309; CHECK-LABEL: zext_v16i8_v16i16:
310; CHECK:       @ %bb.0: @ %entry
311; CHECK-NEXT:    vmov.u8 r0, q0[0]
312; CHECK-NEXT:    vmov.16 q1[0], r0
313; CHECK-NEXT:    vmov.u8 r0, q0[1]
314; CHECK-NEXT:    vmov.16 q1[1], r0
315; CHECK-NEXT:    vmov.u8 r0, q0[2]
316; CHECK-NEXT:    vmov.16 q1[2], r0
317; CHECK-NEXT:    vmov.u8 r0, q0[3]
318; CHECK-NEXT:    vmov.16 q1[3], r0
319; CHECK-NEXT:    vmov.u8 r0, q0[4]
320; CHECK-NEXT:    vmov.16 q1[4], r0
321; CHECK-NEXT:    vmov.u8 r0, q0[5]
322; CHECK-NEXT:    vmov.16 q1[5], r0
323; CHECK-NEXT:    vmov.u8 r0, q0[6]
324; CHECK-NEXT:    vmov.16 q1[6], r0
325; CHECK-NEXT:    vmov.u8 r0, q0[7]
326; CHECK-NEXT:    vmov.16 q1[7], r0
327; CHECK-NEXT:    vmov.u8 r0, q0[8]
328; CHECK-NEXT:    vmovlb.u8 q2, q1
329; CHECK-NEXT:    vmov.16 q1[0], r0
330; CHECK-NEXT:    vmov.u8 r0, q0[9]
331; CHECK-NEXT:    vmov.16 q1[1], r0
332; CHECK-NEXT:    vmov.u8 r0, q0[10]
333; CHECK-NEXT:    vmov.16 q1[2], r0
334; CHECK-NEXT:    vmov.u8 r0, q0[11]
335; CHECK-NEXT:    vmov.16 q1[3], r0
336; CHECK-NEXT:    vmov.u8 r0, q0[12]
337; CHECK-NEXT:    vmov.16 q1[4], r0
338; CHECK-NEXT:    vmov.u8 r0, q0[13]
339; CHECK-NEXT:    vmov.16 q1[5], r0
340; CHECK-NEXT:    vmov.u8 r0, q0[14]
341; CHECK-NEXT:    vmov.16 q1[6], r0
342; CHECK-NEXT:    vmov.u8 r0, q0[15]
343; CHECK-NEXT:    vmov.16 q1[7], r0
344; CHECK-NEXT:    vmov q0, q2
345; CHECK-NEXT:    vmovlb.u8 q1, q1
346; CHECK-NEXT:    bx lr
347entry:
348  %0 = zext <16 x i8> %src to <16 x i16>
349  ret <16 x i16> %0
350}
351
352define arm_aapcs_vfpcc <8 x i32> @zext_v8i16_v8i32(<8 x i16> %src) {
353; CHECK-LABEL: zext_v8i16_v8i32:
354; CHECK:       @ %bb.0: @ %entry
355; CHECK-NEXT:    vmov.u16 r0, q0[0]
356; CHECK-NEXT:    vmov.32 q1[0], r0
357; CHECK-NEXT:    vmov.u16 r0, q0[1]
358; CHECK-NEXT:    vmov.32 q1[1], r0
359; CHECK-NEXT:    vmov.u16 r0, q0[2]
360; CHECK-NEXT:    vmov.32 q1[2], r0
361; CHECK-NEXT:    vmov.u16 r0, q0[3]
362; CHECK-NEXT:    vmov.32 q1[3], r0
363; CHECK-NEXT:    vmov.u16 r0, q0[4]
364; CHECK-NEXT:    vmovlb.u16 q2, q1
365; CHECK-NEXT:    vmov.32 q1[0], r0
366; CHECK-NEXT:    vmov.u16 r0, q0[5]
367; CHECK-NEXT:    vmov.32 q1[1], r0
368; CHECK-NEXT:    vmov.u16 r0, q0[6]
369; CHECK-NEXT:    vmov.32 q1[2], r0
370; CHECK-NEXT:    vmov.u16 r0, q0[7]
371; CHECK-NEXT:    vmov.32 q1[3], r0
372; CHECK-NEXT:    vmov q0, q2
373; CHECK-NEXT:    vmovlb.u16 q1, q1
374; CHECK-NEXT:    bx lr
375entry:
376  %0 = zext <8 x i16> %src to <8 x i32>
377  ret <8 x i32> %0
378}
379
380define arm_aapcs_vfpcc <16 x i32> @zext_v16i8_v16i32(<16 x i8> %src) {
381; CHECK-LABEL: zext_v16i8_v16i32:
382; CHECK:       @ %bb.0: @ %entry
383; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
384; CHECK-NEXT:    vpush {d8, d9, d10, d11}
385; CHECK-NEXT:    vmov.u8 r0, q0[0]
386; CHECK-NEXT:    vmov.i32 q3, #0xff
387; CHECK-NEXT:    vmov.32 q1[0], r0
388; CHECK-NEXT:    vmov.u8 r0, q0[1]
389; CHECK-NEXT:    vmov.32 q1[1], r0
390; CHECK-NEXT:    vmov.u8 r0, q0[2]
391; CHECK-NEXT:    vmov.32 q1[2], r0
392; CHECK-NEXT:    vmov.u8 r0, q0[3]
393; CHECK-NEXT:    vmov.32 q1[3], r0
394; CHECK-NEXT:    vmov.u8 r0, q0[4]
395; CHECK-NEXT:    vand q4, q1, q3
396; CHECK-NEXT:    vmov.32 q1[0], r0
397; CHECK-NEXT:    vmov.u8 r0, q0[5]
398; CHECK-NEXT:    vmov.32 q1[1], r0
399; CHECK-NEXT:    vmov.u8 r0, q0[6]
400; CHECK-NEXT:    vmov.32 q1[2], r0
401; CHECK-NEXT:    vmov.u8 r0, q0[7]
402; CHECK-NEXT:    vmov.32 q1[3], r0
403; CHECK-NEXT:    vmov.u8 r0, q0[8]
404; CHECK-NEXT:    vmov.32 q2[0], r0
405; CHECK-NEXT:    vmov.u8 r0, q0[9]
406; CHECK-NEXT:    vmov.32 q2[1], r0
407; CHECK-NEXT:    vmov.u8 r0, q0[10]
408; CHECK-NEXT:    vmov.32 q2[2], r0
409; CHECK-NEXT:    vmov.u8 r0, q0[11]
410; CHECK-NEXT:    vmov.32 q2[3], r0
411; CHECK-NEXT:    vmov.u8 r0, q0[12]
412; CHECK-NEXT:    vmov.32 q5[0], r0
413; CHECK-NEXT:    vmov.u8 r0, q0[13]
414; CHECK-NEXT:    vmov.32 q5[1], r0
415; CHECK-NEXT:    vmov.u8 r0, q0[14]
416; CHECK-NEXT:    vmov.32 q5[2], r0
417; CHECK-NEXT:    vmov.u8 r0, q0[15]
418; CHECK-NEXT:    vmov.32 q5[3], r0
419; CHECK-NEXT:    vand q1, q1, q3
420; CHECK-NEXT:    vand q2, q2, q3
421; CHECK-NEXT:    vand q3, q5, q3
422; CHECK-NEXT:    vmov q0, q4
423; CHECK-NEXT:    vpop {d8, d9, d10, d11}
424; CHECK-NEXT:    bx lr
425entry:
426  %0 = zext <16 x i8> %src to <16 x i32>
427  ret <16 x i32> %0
428}
429
430define arm_aapcs_vfpcc <2 x i64> @zext_v2i32_v2i64(<2 x i32> %src) {
431; CHECK-LABEL: zext_v2i32_v2i64:
432; CHECK:       @ %bb.0: @ %entry
433; CHECK-NEXT:    vmov.i64 q1, #0xffffffff
434; CHECK-NEXT:    vand q0, q0, q1
435; CHECK-NEXT:    bx lr
436entry:
437  %0 = zext <2 x i32> %src to <2 x i64>
438  ret <2 x i64> %0
439}
440
441
442define arm_aapcs_vfpcc <8 x i8> @trunc_v8i16_v8i8(<8 x i16> %src) {
443; CHECK-LABEL: trunc_v8i16_v8i8:
444; CHECK:       @ %bb.0: @ %entry
445; CHECK-NEXT:    bx lr
446entry:
447  %0 = trunc <8 x i16> %src to <8 x i8>
448  ret <8 x i8> %0
449}
450
451define arm_aapcs_vfpcc <4 x i16> @trunc_v4i32_v4i16(<4 x i32> %src) {
452; CHECK-LABEL: trunc_v4i32_v4i16:
453; CHECK:       @ %bb.0: @ %entry
454; CHECK-NEXT:    bx lr
455entry:
456  %0 = trunc <4 x i32> %src to <4 x i16>
457  ret <4 x i16> %0
458}
459
460define arm_aapcs_vfpcc <4 x i8> @trunc_v4i32_v4i8(<4 x i32> %src) {
461; CHECK-LABEL: trunc_v4i32_v4i8:
462; CHECK:       @ %bb.0: @ %entry
463; CHECK-NEXT:    bx lr
464entry:
465  %0 = trunc <4 x i32> %src to <4 x i8>
466  ret <4 x i8> %0
467}
468
469define arm_aapcs_vfpcc <16 x i8> @trunc_v16i16_v16i8(<16 x i16> %src) {
470; CHECK-LABEL: trunc_v16i16_v16i8:
471; CHECK:       @ %bb.0: @ %entry
472; CHECK-NEXT:    vmov q2, q0
473; CHECK-NEXT:    vmov.u16 r0, q0[0]
474; CHECK-NEXT:    vmov.8 q0[0], r0
475; CHECK-NEXT:    vmov.u16 r0, q2[1]
476; CHECK-NEXT:    vmov.8 q0[1], r0
477; CHECK-NEXT:    vmov.u16 r0, q2[2]
478; CHECK-NEXT:    vmov.8 q0[2], r0
479; CHECK-NEXT:    vmov.u16 r0, q2[3]
480; CHECK-NEXT:    vmov.8 q0[3], r0
481; CHECK-NEXT:    vmov.u16 r0, q2[4]
482; CHECK-NEXT:    vmov.8 q0[4], r0
483; CHECK-NEXT:    vmov.u16 r0, q2[5]
484; CHECK-NEXT:    vmov.8 q0[5], r0
485; CHECK-NEXT:    vmov.u16 r0, q2[6]
486; CHECK-NEXT:    vmov.8 q0[6], r0
487; CHECK-NEXT:    vmov.u16 r0, q2[7]
488; CHECK-NEXT:    vmov.8 q0[7], r0
489; CHECK-NEXT:    vmov.u16 r0, q1[0]
490; CHECK-NEXT:    vmov.8 q0[8], r0
491; CHECK-NEXT:    vmov.u16 r0, q1[1]
492; CHECK-NEXT:    vmov.8 q0[9], r0
493; CHECK-NEXT:    vmov.u16 r0, q1[2]
494; CHECK-NEXT:    vmov.8 q0[10], r0
495; CHECK-NEXT:    vmov.u16 r0, q1[3]
496; CHECK-NEXT:    vmov.8 q0[11], r0
497; CHECK-NEXT:    vmov.u16 r0, q1[4]
498; CHECK-NEXT:    vmov.8 q0[12], r0
499; CHECK-NEXT:    vmov.u16 r0, q1[5]
500; CHECK-NEXT:    vmov.8 q0[13], r0
501; CHECK-NEXT:    vmov.u16 r0, q1[6]
502; CHECK-NEXT:    vmov.8 q0[14], r0
503; CHECK-NEXT:    vmov.u16 r0, q1[7]
504; CHECK-NEXT:    vmov.8 q0[15], r0
505; CHECK-NEXT:    bx lr
506entry:
507  %0 = trunc <16 x i16> %src to <16 x i8>
508  ret <16 x i8> %0
509}
510
511define arm_aapcs_vfpcc <8 x i16> @trunc_v8i32_v8i16(<8 x i32> %src) {
512; CHECK-LABEL: trunc_v8i32_v8i16:
513; CHECK:       @ %bb.0: @ %entry
514; CHECK-NEXT:    vmov q2, q0
515; CHECK-NEXT:    vmov r0, s8
516; CHECK-NEXT:    vmov.16 q0[0], r0
517; CHECK-NEXT:    vmov r0, s9
518; CHECK-NEXT:    vmov.16 q0[1], r0
519; CHECK-NEXT:    vmov r0, s10
520; CHECK-NEXT:    vmov.16 q0[2], r0
521; CHECK-NEXT:    vmov r0, s11
522; CHECK-NEXT:    vmov.16 q0[3], r0
523; CHECK-NEXT:    vmov r0, s4
524; CHECK-NEXT:    vmov.16 q0[4], r0
525; CHECK-NEXT:    vmov r0, s5
526; CHECK-NEXT:    vmov.16 q0[5], r0
527; CHECK-NEXT:    vmov r0, s6
528; CHECK-NEXT:    vmov.16 q0[6], r0
529; CHECK-NEXT:    vmov r0, s7
530; CHECK-NEXT:    vmov.16 q0[7], r0
531; CHECK-NEXT:    bx lr
532entry:
533  %0 = trunc <8 x i32> %src to <8 x i16>
534  ret <8 x i16> %0
535}
536
537define arm_aapcs_vfpcc <16 x i8> @trunc_v16i32_v16i8(<16 x i32> %src) {
538; CHECK-LABEL: trunc_v16i32_v16i8:
539; CHECK:       @ %bb.0: @ %entry
540; CHECK-NEXT:    .vsave {d8, d9}
541; CHECK-NEXT:    vpush {d8, d9}
542; CHECK-NEXT:    vmov q4, q0
543; CHECK-NEXT:    vmov r0, s16
544; CHECK-NEXT:    vmov.8 q0[0], r0
545; CHECK-NEXT:    vmov r0, s17
546; CHECK-NEXT:    vmov.8 q0[1], r0
547; CHECK-NEXT:    vmov r0, s18
548; CHECK-NEXT:    vmov.8 q0[2], r0
549; CHECK-NEXT:    vmov r0, s19
550; CHECK-NEXT:    vmov.8 q0[3], r0
551; CHECK-NEXT:    vmov r0, s4
552; CHECK-NEXT:    vmov.8 q0[4], r0
553; CHECK-NEXT:    vmov r0, s5
554; CHECK-NEXT:    vmov.8 q0[5], r0
555; CHECK-NEXT:    vmov r0, s6
556; CHECK-NEXT:    vmov.8 q0[6], r0
557; CHECK-NEXT:    vmov r0, s7
558; CHECK-NEXT:    vmov.8 q0[7], r0
559; CHECK-NEXT:    vmov r0, s8
560; CHECK-NEXT:    vmov.8 q0[8], r0
561; CHECK-NEXT:    vmov r0, s9
562; CHECK-NEXT:    vmov.8 q0[9], r0
563; CHECK-NEXT:    vmov r0, s10
564; CHECK-NEXT:    vmov.8 q0[10], r0
565; CHECK-NEXT:    vmov r0, s11
566; CHECK-NEXT:    vmov.8 q0[11], r0
567; CHECK-NEXT:    vmov r0, s12
568; CHECK-NEXT:    vmov.8 q0[12], r0
569; CHECK-NEXT:    vmov r0, s13
570; CHECK-NEXT:    vmov.8 q0[13], r0
571; CHECK-NEXT:    vmov r0, s14
572; CHECK-NEXT:    vmov.8 q0[14], r0
573; CHECK-NEXT:    vmov r0, s15
574; CHECK-NEXT:    vmov.8 q0[15], r0
575; CHECK-NEXT:    vpop {d8, d9}
576; CHECK-NEXT:    bx lr
577entry:
578  %0 = trunc <16 x i32> %src to <16 x i8>
579  ret <16 x i8> %0
580}
581
582define arm_aapcs_vfpcc <2 x i32> @trunc_v2i64_v2i32(<2 x i64> %src) {
583; CHECK-LABEL: trunc_v2i64_v2i32:
584; CHECK:       @ %bb.0: @ %entry
585; CHECK-NEXT:    bx lr
586entry:
587  %0 = trunc <2 x i64> %src to <2 x i32>
588  ret <2 x i32> %0
589}
590
591