1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s 3 4define arm_aapcs_vfpcc <4 x i32> @vcmp_eq_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 5; CHECK-LABEL: vcmp_eq_v4i32: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vcmp.i32 eq, q0, r0 8; CHECK-NEXT: vpsel q0, q1, q2 9; CHECK-NEXT: bx lr 10entry: 11 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 12 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 13 %c = icmp eq <4 x i32> %src, %sp 14 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 15 ret <4 x i32> %s 16} 17 18define arm_aapcs_vfpcc <4 x i32> @vcmp_ne_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 19; CHECK-LABEL: vcmp_ne_v4i32: 20; CHECK: @ %bb.0: @ %entry 21; CHECK-NEXT: vcmp.i32 ne, q0, r0 22; CHECK-NEXT: vpsel q0, q1, q2 23; CHECK-NEXT: bx lr 24entry: 25 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 26 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 27 %c = icmp ne <4 x i32> %src, %sp 28 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 29 ret <4 x i32> %s 30} 31 32define arm_aapcs_vfpcc <4 x i32> @vcmp_sgt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 33; CHECK-LABEL: vcmp_sgt_v4i32: 34; CHECK: @ %bb.0: @ %entry 35; CHECK-NEXT: vcmp.s32 gt, q0, r0 36; CHECK-NEXT: vpsel q0, q1, q2 37; CHECK-NEXT: bx lr 38entry: 39 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 40 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 41 %c = icmp sgt <4 x i32> %src, %sp 42 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 43 ret <4 x i32> %s 44} 45 46define arm_aapcs_vfpcc <4 x i32> @vcmp_sge_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 47; CHECK-LABEL: vcmp_sge_v4i32: 48; CHECK: @ %bb.0: @ %entry 49; CHECK-NEXT: vcmp.s32 ge, q0, r0 50; CHECK-NEXT: vpsel q0, q1, q2 51; CHECK-NEXT: bx lr 52entry: 53 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 54 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 55 %c = icmp sge <4 x i32> %src, %sp 56 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 57 ret <4 x i32> %s 58} 59 60define arm_aapcs_vfpcc <4 x i32> @vcmp_slt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 61; CHECK-LABEL: vcmp_slt_v4i32: 62; CHECK: @ %bb.0: @ %entry 63; CHECK-NEXT: vcmp.s32 lt, q0, r0 64; CHECK-NEXT: vpsel q0, q1, q2 65; CHECK-NEXT: bx lr 66entry: 67 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 68 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 69 %c = icmp slt <4 x i32> %src, %sp 70 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 71 ret <4 x i32> %s 72} 73 74define arm_aapcs_vfpcc <4 x i32> @vcmp_sle_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 75; CHECK-LABEL: vcmp_sle_v4i32: 76; CHECK: @ %bb.0: @ %entry 77; CHECK-NEXT: vcmp.s32 le, q0, r0 78; CHECK-NEXT: vpsel q0, q1, q2 79; CHECK-NEXT: bx lr 80entry: 81 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 82 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 83 %c = icmp sle <4 x i32> %src, %sp 84 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 85 ret <4 x i32> %s 86} 87 88define arm_aapcs_vfpcc <4 x i32> @vcmp_ugt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 89; CHECK-LABEL: vcmp_ugt_v4i32: 90; CHECK: @ %bb.0: @ %entry 91; CHECK-NEXT: vcmp.u32 hi, q0, r0 92; CHECK-NEXT: vpsel q0, q1, q2 93; CHECK-NEXT: bx lr 94entry: 95 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 96 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 97 %c = icmp ugt <4 x i32> %src, %sp 98 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 99 ret <4 x i32> %s 100} 101 102define arm_aapcs_vfpcc <4 x i32> @vcmp_uge_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 103; CHECK-LABEL: vcmp_uge_v4i32: 104; CHECK: @ %bb.0: @ %entry 105; CHECK-NEXT: vcmp.u32 cs, q0, r0 106; CHECK-NEXT: vpsel q0, q1, q2 107; CHECK-NEXT: bx lr 108entry: 109 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 110 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 111 %c = icmp uge <4 x i32> %src, %sp 112 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 113 ret <4 x i32> %s 114} 115 116define arm_aapcs_vfpcc <4 x i32> @vcmp_ult_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 117; CHECK-LABEL: vcmp_ult_v4i32: 118; CHECK: @ %bb.0: @ %entry 119; CHECK-NEXT: vdup.32 q3, r0 120; CHECK-NEXT: vcmp.u32 hi, q3, q0 121; CHECK-NEXT: vpsel q0, q1, q2 122; CHECK-NEXT: bx lr 123entry: 124 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 125 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 126 %c = icmp ult <4 x i32> %src, %sp 127 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 128 ret <4 x i32> %s 129} 130 131define arm_aapcs_vfpcc <4 x i32> @vcmp_ule_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 132; CHECK-LABEL: vcmp_ule_v4i32: 133; CHECK: @ %bb.0: @ %entry 134; CHECK-NEXT: vdup.32 q3, r0 135; CHECK-NEXT: vcmp.u32 cs, q3, q0 136; CHECK-NEXT: vpsel q0, q1, q2 137; CHECK-NEXT: bx lr 138entry: 139 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 140 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 141 %c = icmp ule <4 x i32> %src, %sp 142 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 143 ret <4 x i32> %s 144} 145 146 147define arm_aapcs_vfpcc <8 x i16> @vcmp_eq_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 148; CHECK-LABEL: vcmp_eq_v8i16: 149; CHECK: @ %bb.0: @ %entry 150; CHECK-NEXT: vcmp.i16 eq, q0, r0 151; CHECK-NEXT: vpsel q0, q1, q2 152; CHECK-NEXT: bx lr 153entry: 154 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 155 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 156 %c = icmp eq <8 x i16> %src, %sp 157 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 158 ret <8 x i16> %s 159} 160 161define arm_aapcs_vfpcc <8 x i16> @vcmp_ne_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 162; CHECK-LABEL: vcmp_ne_v8i16: 163; CHECK: @ %bb.0: @ %entry 164; CHECK-NEXT: vcmp.i16 ne, q0, r0 165; CHECK-NEXT: vpsel q0, q1, q2 166; CHECK-NEXT: bx lr 167entry: 168 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 169 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 170 %c = icmp ne <8 x i16> %src, %sp 171 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 172 ret <8 x i16> %s 173} 174 175define arm_aapcs_vfpcc <8 x i16> @vcmp_sgt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 176; CHECK-LABEL: vcmp_sgt_v8i16: 177; CHECK: @ %bb.0: @ %entry 178; CHECK-NEXT: vcmp.s16 gt, q0, r0 179; CHECK-NEXT: vpsel q0, q1, q2 180; CHECK-NEXT: bx lr 181entry: 182 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 183 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 184 %c = icmp sgt <8 x i16> %src, %sp 185 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 186 ret <8 x i16> %s 187} 188 189define arm_aapcs_vfpcc <8 x i16> @vcmp_sge_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 190; CHECK-LABEL: vcmp_sge_v8i16: 191; CHECK: @ %bb.0: @ %entry 192; CHECK-NEXT: vcmp.s16 ge, q0, r0 193; CHECK-NEXT: vpsel q0, q1, q2 194; CHECK-NEXT: bx lr 195entry: 196 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 197 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 198 %c = icmp sge <8 x i16> %src, %sp 199 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 200 ret <8 x i16> %s 201} 202 203define arm_aapcs_vfpcc <8 x i16> @vcmp_slt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 204; CHECK-LABEL: vcmp_slt_v8i16: 205; CHECK: @ %bb.0: @ %entry 206; CHECK-NEXT: vcmp.s16 lt, q0, r0 207; CHECK-NEXT: vpsel q0, q1, q2 208; CHECK-NEXT: bx lr 209entry: 210 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 211 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 212 %c = icmp slt <8 x i16> %src, %sp 213 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 214 ret <8 x i16> %s 215} 216 217define arm_aapcs_vfpcc <8 x i16> @vcmp_sle_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 218; CHECK-LABEL: vcmp_sle_v8i16: 219; CHECK: @ %bb.0: @ %entry 220; CHECK-NEXT: vcmp.s16 le, q0, r0 221; CHECK-NEXT: vpsel q0, q1, q2 222; CHECK-NEXT: bx lr 223entry: 224 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 225 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 226 %c = icmp sle <8 x i16> %src, %sp 227 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 228 ret <8 x i16> %s 229} 230 231define arm_aapcs_vfpcc <8 x i16> @vcmp_ugt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 232; CHECK-LABEL: vcmp_ugt_v8i16: 233; CHECK: @ %bb.0: @ %entry 234; CHECK-NEXT: vcmp.u16 hi, q0, r0 235; CHECK-NEXT: vpsel q0, q1, q2 236; CHECK-NEXT: bx lr 237entry: 238 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 239 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 240 %c = icmp ugt <8 x i16> %src, %sp 241 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 242 ret <8 x i16> %s 243} 244 245define arm_aapcs_vfpcc <8 x i16> @vcmp_uge_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 246; CHECK-LABEL: vcmp_uge_v8i16: 247; CHECK: @ %bb.0: @ %entry 248; CHECK-NEXT: vcmp.u16 cs, q0, r0 249; CHECK-NEXT: vpsel q0, q1, q2 250; CHECK-NEXT: bx lr 251entry: 252 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 253 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 254 %c = icmp uge <8 x i16> %src, %sp 255 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 256 ret <8 x i16> %s 257} 258 259define arm_aapcs_vfpcc <8 x i16> @vcmp_ult_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 260; CHECK-LABEL: vcmp_ult_v8i16: 261; CHECK: @ %bb.0: @ %entry 262; CHECK-NEXT: vdup.16 q3, r0 263; CHECK-NEXT: vcmp.u16 hi, q3, q0 264; CHECK-NEXT: vpsel q0, q1, q2 265; CHECK-NEXT: bx lr 266entry: 267 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 268 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 269 %c = icmp ult <8 x i16> %src, %sp 270 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 271 ret <8 x i16> %s 272} 273 274define arm_aapcs_vfpcc <8 x i16> @vcmp_ule_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 275; CHECK-LABEL: vcmp_ule_v8i16: 276; CHECK: @ %bb.0: @ %entry 277; CHECK-NEXT: vdup.16 q3, r0 278; CHECK-NEXT: vcmp.u16 cs, q3, q0 279; CHECK-NEXT: vpsel q0, q1, q2 280; CHECK-NEXT: bx lr 281entry: 282 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 283 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 284 %c = icmp ule <8 x i16> %src, %sp 285 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 286 ret <8 x i16> %s 287} 288 289 290define arm_aapcs_vfpcc <16 x i8> @vcmp_eq_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 291; CHECK-LABEL: vcmp_eq_v16i8: 292; CHECK: @ %bb.0: @ %entry 293; CHECK-NEXT: vcmp.i8 eq, q0, r0 294; CHECK-NEXT: vpsel q0, q1, q2 295; CHECK-NEXT: bx lr 296entry: 297 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 298 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 299 %c = icmp eq <16 x i8> %src, %sp 300 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 301 ret <16 x i8> %s 302} 303 304define arm_aapcs_vfpcc <16 x i8> @vcmp_ne_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 305; CHECK-LABEL: vcmp_ne_v16i8: 306; CHECK: @ %bb.0: @ %entry 307; CHECK-NEXT: vcmp.i8 ne, q0, r0 308; CHECK-NEXT: vpsel q0, q1, q2 309; CHECK-NEXT: bx lr 310entry: 311 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 312 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 313 %c = icmp ne <16 x i8> %src, %sp 314 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 315 ret <16 x i8> %s 316} 317 318define arm_aapcs_vfpcc <16 x i8> @vcmp_sgt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 319; CHECK-LABEL: vcmp_sgt_v16i8: 320; CHECK: @ %bb.0: @ %entry 321; CHECK-NEXT: vcmp.s8 gt, q0, r0 322; CHECK-NEXT: vpsel q0, q1, q2 323; CHECK-NEXT: bx lr 324entry: 325 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 326 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 327 %c = icmp sgt <16 x i8> %src, %sp 328 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 329 ret <16 x i8> %s 330} 331 332define arm_aapcs_vfpcc <16 x i8> @vcmp_sge_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 333; CHECK-LABEL: vcmp_sge_v16i8: 334; CHECK: @ %bb.0: @ %entry 335; CHECK-NEXT: vcmp.s8 ge, q0, r0 336; CHECK-NEXT: vpsel q0, q1, q2 337; CHECK-NEXT: bx lr 338entry: 339 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 340 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 341 %c = icmp sge <16 x i8> %src, %sp 342 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 343 ret <16 x i8> %s 344} 345 346define arm_aapcs_vfpcc <16 x i8> @vcmp_slt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 347; CHECK-LABEL: vcmp_slt_v16i8: 348; CHECK: @ %bb.0: @ %entry 349; CHECK-NEXT: vcmp.s8 lt, q0, r0 350; CHECK-NEXT: vpsel q0, q1, q2 351; CHECK-NEXT: bx lr 352entry: 353 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 354 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 355 %c = icmp slt <16 x i8> %src, %sp 356 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 357 ret <16 x i8> %s 358} 359 360define arm_aapcs_vfpcc <16 x i8> @vcmp_sle_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 361; CHECK-LABEL: vcmp_sle_v16i8: 362; CHECK: @ %bb.0: @ %entry 363; CHECK-NEXT: vcmp.s8 le, q0, r0 364; CHECK-NEXT: vpsel q0, q1, q2 365; CHECK-NEXT: bx lr 366entry: 367 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 368 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 369 %c = icmp sle <16 x i8> %src, %sp 370 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 371 ret <16 x i8> %s 372} 373 374define arm_aapcs_vfpcc <16 x i8> @vcmp_ugt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 375; CHECK-LABEL: vcmp_ugt_v16i8: 376; CHECK: @ %bb.0: @ %entry 377; CHECK-NEXT: vcmp.u8 hi, q0, r0 378; CHECK-NEXT: vpsel q0, q1, q2 379; CHECK-NEXT: bx lr 380entry: 381 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 382 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 383 %c = icmp ugt <16 x i8> %src, %sp 384 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 385 ret <16 x i8> %s 386} 387 388define arm_aapcs_vfpcc <16 x i8> @vcmp_uge_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 389; CHECK-LABEL: vcmp_uge_v16i8: 390; CHECK: @ %bb.0: @ %entry 391; CHECK-NEXT: vcmp.u8 cs, q0, r0 392; CHECK-NEXT: vpsel q0, q1, q2 393; CHECK-NEXT: bx lr 394entry: 395 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 396 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 397 %c = icmp uge <16 x i8> %src, %sp 398 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 399 ret <16 x i8> %s 400} 401 402define arm_aapcs_vfpcc <16 x i8> @vcmp_ult_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 403; CHECK-LABEL: vcmp_ult_v16i8: 404; CHECK: @ %bb.0: @ %entry 405; CHECK-NEXT: vdup.8 q3, r0 406; CHECK-NEXT: vcmp.u8 hi, q3, q0 407; CHECK-NEXT: vpsel q0, q1, q2 408; CHECK-NEXT: bx lr 409entry: 410 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 411 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 412 %c = icmp ult <16 x i8> %src, %sp 413 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 414 ret <16 x i8> %s 415} 416 417define arm_aapcs_vfpcc <16 x i8> @vcmp_ule_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 418; CHECK-LABEL: vcmp_ule_v16i8: 419; CHECK: @ %bb.0: @ %entry 420; CHECK-NEXT: vdup.8 q3, r0 421; CHECK-NEXT: vcmp.u8 cs, q3, q0 422; CHECK-NEXT: vpsel q0, q1, q2 423; CHECK-NEXT: bx lr 424entry: 425 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 426 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 427 %c = icmp ule <16 x i8> %src, %sp 428 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 429 ret <16 x i8> %s 430} 431 432 433define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, i64 %src2, <2 x i64> %a, <2 x i64> %b) { 434; CHECK-LABEL: vcmp_eq_v2i64: 435; CHECK: @ %bb.0: @ %entry 436; CHECK-NEXT: vmov r2, s1 437; CHECK-NEXT: vmov r3, s0 438; CHECK-NEXT: eors r2, r1 439; CHECK-NEXT: eors r3, r0 440; CHECK-NEXT: orrs r2, r3 441; CHECK-NEXT: cset r2, eq 442; CHECK-NEXT: tst.w r2, #1 443; CHECK-NEXT: csetm r2, ne 444; CHECK-NEXT: vmov.32 q3[0], r2 445; CHECK-NEXT: vmov.32 q3[1], r2 446; CHECK-NEXT: vmov r2, s3 447; CHECK-NEXT: eors r1, r2 448; CHECK-NEXT: vmov r2, s2 449; CHECK-NEXT: eors r0, r2 450; CHECK-NEXT: orrs r0, r1 451; CHECK-NEXT: cset r0, eq 452; CHECK-NEXT: tst.w r0, #1 453; CHECK-NEXT: csetm r0, ne 454; CHECK-NEXT: vmov.32 q3[2], r0 455; CHECK-NEXT: vmov.32 q3[3], r0 456; CHECK-NEXT: vbic q0, q2, q3 457; CHECK-NEXT: vand q1, q1, q3 458; CHECK-NEXT: vorr q0, q1, q0 459; CHECK-NEXT: bx lr 460entry: 461 %i = insertelement <2 x i64> undef, i64 %src2, i32 0 462 %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer 463 %c = icmp eq <2 x i64> %src, %sp 464 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b 465 ret <2 x i64> %s 466} 467 468define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, i64 %src2, <2 x i32> %a, <2 x i32> %b) { 469; CHECK-LABEL: vcmp_eq_v2i32: 470; CHECK: @ %bb.0: @ %entry 471; CHECK-NEXT: vmov r2, s1 472; CHECK-NEXT: vmov r3, s0 473; CHECK-NEXT: eors r2, r1 474; CHECK-NEXT: eors r3, r0 475; CHECK-NEXT: orrs r2, r3 476; CHECK-NEXT: cset r2, eq 477; CHECK-NEXT: tst.w r2, #1 478; CHECK-NEXT: csetm r2, ne 479; CHECK-NEXT: vmov.32 q3[0], r2 480; CHECK-NEXT: vmov.32 q3[1], r2 481; CHECK-NEXT: vmov r2, s3 482; CHECK-NEXT: eors r1, r2 483; CHECK-NEXT: vmov r2, s2 484; CHECK-NEXT: eors r0, r2 485; CHECK-NEXT: orrs r0, r1 486; CHECK-NEXT: cset r0, eq 487; CHECK-NEXT: tst.w r0, #1 488; CHECK-NEXT: csetm r0, ne 489; CHECK-NEXT: vmov.32 q3[2], r0 490; CHECK-NEXT: vmov.32 q3[3], r0 491; CHECK-NEXT: vbic q0, q2, q3 492; CHECK-NEXT: vand q1, q1, q3 493; CHECK-NEXT: vorr q0, q1, q0 494; CHECK-NEXT: bx lr 495entry: 496 %i = insertelement <2 x i64> undef, i64 %src2, i32 0 497 %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer 498 %c = icmp eq <2 x i64> %src, %sp 499 %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b 500 ret <2 x i32> %s 501} 502 503define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) { 504; CHECK-LABEL: vcmp_multi_v2i32: 505; CHECK: @ %bb.0: 506; CHECK-NEXT: .save {r7, lr} 507; CHECK-NEXT: push {r7, lr} 508; CHECK-NEXT: .vsave {d8, d9, d10, d11} 509; CHECK-NEXT: vpush {d8, d9, d10, d11} 510; CHECK-NEXT: vmov r0, s1 511; CHECK-NEXT: movs r3, #0 512; CHECK-NEXT: vmov r1, s0 513; CHECK-NEXT: vmov r2, s8 514; CHECK-NEXT: orrs r0, r1 515; CHECK-NEXT: vmov r1, s2 516; CHECK-NEXT: cset r0, eq 517; CHECK-NEXT: tst.w r0, #1 518; CHECK-NEXT: csetm r0, ne 519; CHECK-NEXT: vmov.32 q3[0], r0 520; CHECK-NEXT: vmov.32 q3[1], r0 521; CHECK-NEXT: vmov r0, s3 522; CHECK-NEXT: orrs r0, r1 523; CHECK-NEXT: cset r0, eq 524; CHECK-NEXT: tst.w r0, #1 525; CHECK-NEXT: csetm r0, ne 526; CHECK-NEXT: vmov.32 q3[2], r0 527; CHECK-NEXT: vmov.32 q3[3], r0 528; CHECK-NEXT: vbic q0, q2, q3 529; CHECK-NEXT: vmov lr, s0 530; CHECK-NEXT: subs.w r1, lr, r2 531; CHECK-NEXT: asr.w r12, lr, #31 532; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31 533; CHECK-NEXT: mov.w r1, #0 534; CHECK-NEXT: vmov r2, s10 535; CHECK-NEXT: it lt 536; CHECK-NEXT: movlt r1, #1 537; CHECK-NEXT: cmp r1, #0 538; CHECK-NEXT: csetm r1, ne 539; CHECK-NEXT: vmov.32 q3[0], r1 540; CHECK-NEXT: vmov.32 q3[1], r1 541; CHECK-NEXT: vmov r1, s2 542; CHECK-NEXT: subs r0, r1, r2 543; CHECK-NEXT: asr.w r12, r1, #31 544; CHECK-NEXT: sbcs.w r0, r12, r2, asr #31 545; CHECK-NEXT: it lt 546; CHECK-NEXT: movlt r3, #1 547; CHECK-NEXT: cmp r3, #0 548; CHECK-NEXT: csetm r0, ne 549; CHECK-NEXT: cmp.w lr, #0 550; CHECK-NEXT: vmov.32 q3[2], r0 551; CHECK-NEXT: vmov.32 q3[3], r0 552; CHECK-NEXT: cset r0, ne 553; CHECK-NEXT: tst.w r0, #1 554; CHECK-NEXT: csetm r0, ne 555; CHECK-NEXT: cmp r1, #0 556; CHECK-NEXT: vmov.32 q4[0], r0 557; CHECK-NEXT: vmov.32 q4[1], r0 558; CHECK-NEXT: cset r0, ne 559; CHECK-NEXT: tst.w r0, #1 560; CHECK-NEXT: csetm r0, ne 561; CHECK-NEXT: vmov.32 q4[2], r0 562; CHECK-NEXT: vmov.32 q4[3], r0 563; CHECK-NEXT: vmov r0, s4 564; CHECK-NEXT: cmp r0, #0 565; CHECK-NEXT: cset r0, ne 566; CHECK-NEXT: tst.w r0, #1 567; CHECK-NEXT: csetm r0, ne 568; CHECK-NEXT: vmov.32 q5[0], r0 569; CHECK-NEXT: vmov.32 q5[1], r0 570; CHECK-NEXT: vmov r0, s6 571; CHECK-NEXT: cmp r0, #0 572; CHECK-NEXT: cset r0, ne 573; CHECK-NEXT: tst.w r0, #1 574; CHECK-NEXT: csetm r0, ne 575; CHECK-NEXT: vmov.32 q5[2], r0 576; CHECK-NEXT: vmov.32 q5[3], r0 577; CHECK-NEXT: vand q1, q5, q4 578; CHECK-NEXT: vand q1, q3, q1 579; CHECK-NEXT: vbic q0, q0, q1 580; CHECK-NEXT: vand q1, q2, q1 581; CHECK-NEXT: vorr q0, q1, q0 582; CHECK-NEXT: vpop {d8, d9, d10, d11} 583; CHECK-NEXT: pop {r7, pc} 584 %a4 = icmp eq <2 x i64> %a, zeroinitializer 585 %a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c 586 %a6 = icmp ne <2 x i32> %b, zeroinitializer 587 %a7 = icmp slt <2 x i32> %a5, %c 588 %a8 = icmp ne <2 x i32> %a5, zeroinitializer 589 %a9 = and <2 x i1> %a6, %a8 590 %a10 = and <2 x i1> %a7, %a9 591 %a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5 592 ret <2 x i32> %a11 593} 594 595; Reversed 596 597define arm_aapcs_vfpcc <4 x i32> @vcmp_r_eq_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 598; CHECK-LABEL: vcmp_r_eq_v4i32: 599; CHECK: @ %bb.0: @ %entry 600; CHECK-NEXT: vcmp.i32 eq, q0, r0 601; CHECK-NEXT: vpsel q0, q1, q2 602; CHECK-NEXT: bx lr 603entry: 604 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 605 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 606 %c = icmp eq <4 x i32> %sp, %src 607 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 608 ret <4 x i32> %s 609} 610 611define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ne_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 612; CHECK-LABEL: vcmp_r_ne_v4i32: 613; CHECK: @ %bb.0: @ %entry 614; CHECK-NEXT: vcmp.i32 ne, q0, r0 615; CHECK-NEXT: vpsel q0, q1, q2 616; CHECK-NEXT: bx lr 617entry: 618 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 619 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 620 %c = icmp ne <4 x i32> %sp, %src 621 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 622 ret <4 x i32> %s 623} 624 625define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sgt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 626; CHECK-LABEL: vcmp_r_sgt_v4i32: 627; CHECK: @ %bb.0: @ %entry 628; CHECK-NEXT: vcmp.s32 lt, q0, r0 629; CHECK-NEXT: vpsel q0, q1, q2 630; CHECK-NEXT: bx lr 631entry: 632 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 633 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 634 %c = icmp sgt <4 x i32> %sp, %src 635 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 636 ret <4 x i32> %s 637} 638 639define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sge_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 640; CHECK-LABEL: vcmp_r_sge_v4i32: 641; CHECK: @ %bb.0: @ %entry 642; CHECK-NEXT: vcmp.s32 le, q0, r0 643; CHECK-NEXT: vpsel q0, q1, q2 644; CHECK-NEXT: bx lr 645entry: 646 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 647 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 648 %c = icmp sge <4 x i32> %sp, %src 649 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 650 ret <4 x i32> %s 651} 652 653define arm_aapcs_vfpcc <4 x i32> @vcmp_r_slt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 654; CHECK-LABEL: vcmp_r_slt_v4i32: 655; CHECK: @ %bb.0: @ %entry 656; CHECK-NEXT: vcmp.s32 gt, q0, r0 657; CHECK-NEXT: vpsel q0, q1, q2 658; CHECK-NEXT: bx lr 659entry: 660 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 661 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 662 %c = icmp slt <4 x i32> %sp, %src 663 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 664 ret <4 x i32> %s 665} 666 667define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sle_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 668; CHECK-LABEL: vcmp_r_sle_v4i32: 669; CHECK: @ %bb.0: @ %entry 670; CHECK-NEXT: vcmp.s32 ge, q0, r0 671; CHECK-NEXT: vpsel q0, q1, q2 672; CHECK-NEXT: bx lr 673entry: 674 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 675 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 676 %c = icmp sle <4 x i32> %sp, %src 677 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 678 ret <4 x i32> %s 679} 680 681define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ugt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 682; CHECK-LABEL: vcmp_r_ugt_v4i32: 683; CHECK: @ %bb.0: @ %entry 684; CHECK-NEXT: vdup.32 q3, r0 685; CHECK-NEXT: vcmp.u32 hi, q3, q0 686; CHECK-NEXT: vpsel q0, q1, q2 687; CHECK-NEXT: bx lr 688entry: 689 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 690 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 691 %c = icmp ugt <4 x i32> %sp, %src 692 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 693 ret <4 x i32> %s 694} 695 696define arm_aapcs_vfpcc <4 x i32> @vcmp_r_uge_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 697; CHECK-LABEL: vcmp_r_uge_v4i32: 698; CHECK: @ %bb.0: @ %entry 699; CHECK-NEXT: vdup.32 q3, r0 700; CHECK-NEXT: vcmp.u32 cs, q3, q0 701; CHECK-NEXT: vpsel q0, q1, q2 702; CHECK-NEXT: bx lr 703entry: 704 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 705 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 706 %c = icmp uge <4 x i32> %sp, %src 707 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 708 ret <4 x i32> %s 709} 710 711define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ult_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 712; CHECK-LABEL: vcmp_r_ult_v4i32: 713; CHECK: @ %bb.0: @ %entry 714; CHECK-NEXT: vcmp.u32 hi, q0, r0 715; CHECK-NEXT: vpsel q0, q1, q2 716; CHECK-NEXT: bx lr 717entry: 718 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 719 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 720 %c = icmp ult <4 x i32> %sp, %src 721 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 722 ret <4 x i32> %s 723} 724 725define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ule_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 726; CHECK-LABEL: vcmp_r_ule_v4i32: 727; CHECK: @ %bb.0: @ %entry 728; CHECK-NEXT: vcmp.u32 cs, q0, r0 729; CHECK-NEXT: vpsel q0, q1, q2 730; CHECK-NEXT: bx lr 731entry: 732 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 733 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 734 %c = icmp ule <4 x i32> %sp, %src 735 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b 736 ret <4 x i32> %s 737} 738 739 740define arm_aapcs_vfpcc <8 x i16> @vcmp_r_eq_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 741; CHECK-LABEL: vcmp_r_eq_v8i16: 742; CHECK: @ %bb.0: @ %entry 743; CHECK-NEXT: vcmp.i16 eq, q0, r0 744; CHECK-NEXT: vpsel q0, q1, q2 745; CHECK-NEXT: bx lr 746entry: 747 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 748 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 749 %c = icmp eq <8 x i16> %sp, %src 750 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 751 ret <8 x i16> %s 752} 753 754define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ne_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 755; CHECK-LABEL: vcmp_r_ne_v8i16: 756; CHECK: @ %bb.0: @ %entry 757; CHECK-NEXT: vcmp.i16 ne, q0, r0 758; CHECK-NEXT: vpsel q0, q1, q2 759; CHECK-NEXT: bx lr 760entry: 761 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 762 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 763 %c = icmp ne <8 x i16> %sp, %src 764 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 765 ret <8 x i16> %s 766} 767 768define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sgt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 769; CHECK-LABEL: vcmp_r_sgt_v8i16: 770; CHECK: @ %bb.0: @ %entry 771; CHECK-NEXT: vcmp.s16 lt, q0, r0 772; CHECK-NEXT: vpsel q0, q1, q2 773; CHECK-NEXT: bx lr 774entry: 775 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 776 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 777 %c = icmp sgt <8 x i16> %sp, %src 778 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 779 ret <8 x i16> %s 780} 781 782define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sge_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 783; CHECK-LABEL: vcmp_r_sge_v8i16: 784; CHECK: @ %bb.0: @ %entry 785; CHECK-NEXT: vcmp.s16 le, q0, r0 786; CHECK-NEXT: vpsel q0, q1, q2 787; CHECK-NEXT: bx lr 788entry: 789 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 790 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 791 %c = icmp sge <8 x i16> %sp, %src 792 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 793 ret <8 x i16> %s 794} 795 796define arm_aapcs_vfpcc <8 x i16> @vcmp_r_slt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 797; CHECK-LABEL: vcmp_r_slt_v8i16: 798; CHECK: @ %bb.0: @ %entry 799; CHECK-NEXT: vcmp.s16 gt, q0, r0 800; CHECK-NEXT: vpsel q0, q1, q2 801; CHECK-NEXT: bx lr 802entry: 803 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 804 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 805 %c = icmp slt <8 x i16> %sp, %src 806 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 807 ret <8 x i16> %s 808} 809 810define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sle_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 811; CHECK-LABEL: vcmp_r_sle_v8i16: 812; CHECK: @ %bb.0: @ %entry 813; CHECK-NEXT: vcmp.s16 ge, q0, r0 814; CHECK-NEXT: vpsel q0, q1, q2 815; CHECK-NEXT: bx lr 816entry: 817 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 818 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 819 %c = icmp sle <8 x i16> %sp, %src 820 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 821 ret <8 x i16> %s 822} 823 824define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ugt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 825; CHECK-LABEL: vcmp_r_ugt_v8i16: 826; CHECK: @ %bb.0: @ %entry 827; CHECK-NEXT: vdup.16 q3, r0 828; CHECK-NEXT: vcmp.u16 hi, q3, q0 829; CHECK-NEXT: vpsel q0, q1, q2 830; CHECK-NEXT: bx lr 831entry: 832 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 833 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 834 %c = icmp ugt <8 x i16> %sp, %src 835 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 836 ret <8 x i16> %s 837} 838 839define arm_aapcs_vfpcc <8 x i16> @vcmp_r_uge_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 840; CHECK-LABEL: vcmp_r_uge_v8i16: 841; CHECK: @ %bb.0: @ %entry 842; CHECK-NEXT: vdup.16 q3, r0 843; CHECK-NEXT: vcmp.u16 cs, q3, q0 844; CHECK-NEXT: vpsel q0, q1, q2 845; CHECK-NEXT: bx lr 846entry: 847 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 848 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 849 %c = icmp uge <8 x i16> %sp, %src 850 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 851 ret <8 x i16> %s 852} 853 854define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ult_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 855; CHECK-LABEL: vcmp_r_ult_v8i16: 856; CHECK: @ %bb.0: @ %entry 857; CHECK-NEXT: vcmp.u16 hi, q0, r0 858; CHECK-NEXT: vpsel q0, q1, q2 859; CHECK-NEXT: bx lr 860entry: 861 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 862 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 863 %c = icmp ult <8 x i16> %sp, %src 864 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 865 ret <8 x i16> %s 866} 867 868define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ule_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 869; CHECK-LABEL: vcmp_r_ule_v8i16: 870; CHECK: @ %bb.0: @ %entry 871; CHECK-NEXT: vcmp.u16 cs, q0, r0 872; CHECK-NEXT: vpsel q0, q1, q2 873; CHECK-NEXT: bx lr 874entry: 875 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 876 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 877 %c = icmp ule <8 x i16> %sp, %src 878 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b 879 ret <8 x i16> %s 880} 881 882 883define arm_aapcs_vfpcc <16 x i8> @vcmp_r_eq_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 884; CHECK-LABEL: vcmp_r_eq_v16i8: 885; CHECK: @ %bb.0: @ %entry 886; CHECK-NEXT: vcmp.i8 eq, q0, r0 887; CHECK-NEXT: vpsel q0, q1, q2 888; CHECK-NEXT: bx lr 889entry: 890 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 891 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 892 %c = icmp eq <16 x i8> %sp, %src 893 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 894 ret <16 x i8> %s 895} 896 897define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ne_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 898; CHECK-LABEL: vcmp_r_ne_v16i8: 899; CHECK: @ %bb.0: @ %entry 900; CHECK-NEXT: vcmp.i8 ne, q0, r0 901; CHECK-NEXT: vpsel q0, q1, q2 902; CHECK-NEXT: bx lr 903entry: 904 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 905 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 906 %c = icmp ne <16 x i8> %sp, %src 907 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 908 ret <16 x i8> %s 909} 910 911define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sgt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 912; CHECK-LABEL: vcmp_r_sgt_v16i8: 913; CHECK: @ %bb.0: @ %entry 914; CHECK-NEXT: vcmp.s8 lt, q0, r0 915; CHECK-NEXT: vpsel q0, q1, q2 916; CHECK-NEXT: bx lr 917entry: 918 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 919 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 920 %c = icmp sgt <16 x i8> %sp, %src 921 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 922 ret <16 x i8> %s 923} 924 925define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sge_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 926; CHECK-LABEL: vcmp_r_sge_v16i8: 927; CHECK: @ %bb.0: @ %entry 928; CHECK-NEXT: vcmp.s8 le, q0, r0 929; CHECK-NEXT: vpsel q0, q1, q2 930; CHECK-NEXT: bx lr 931entry: 932 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 933 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 934 %c = icmp sge <16 x i8> %sp, %src 935 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 936 ret <16 x i8> %s 937} 938 939define arm_aapcs_vfpcc <16 x i8> @vcmp_r_slt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 940; CHECK-LABEL: vcmp_r_slt_v16i8: 941; CHECK: @ %bb.0: @ %entry 942; CHECK-NEXT: vcmp.s8 gt, q0, r0 943; CHECK-NEXT: vpsel q0, q1, q2 944; CHECK-NEXT: bx lr 945entry: 946 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 947 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 948 %c = icmp slt <16 x i8> %sp, %src 949 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 950 ret <16 x i8> %s 951} 952 953define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sle_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 954; CHECK-LABEL: vcmp_r_sle_v16i8: 955; CHECK: @ %bb.0: @ %entry 956; CHECK-NEXT: vcmp.s8 ge, q0, r0 957; CHECK-NEXT: vpsel q0, q1, q2 958; CHECK-NEXT: bx lr 959entry: 960 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 961 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 962 %c = icmp sle <16 x i8> %sp, %src 963 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 964 ret <16 x i8> %s 965} 966 967define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ugt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 968; CHECK-LABEL: vcmp_r_ugt_v16i8: 969; CHECK: @ %bb.0: @ %entry 970; CHECK-NEXT: vdup.8 q3, r0 971; CHECK-NEXT: vcmp.u8 hi, q3, q0 972; CHECK-NEXT: vpsel q0, q1, q2 973; CHECK-NEXT: bx lr 974entry: 975 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 976 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 977 %c = icmp ugt <16 x i8> %sp, %src 978 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 979 ret <16 x i8> %s 980} 981 982define arm_aapcs_vfpcc <16 x i8> @vcmp_r_uge_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 983; CHECK-LABEL: vcmp_r_uge_v16i8: 984; CHECK: @ %bb.0: @ %entry 985; CHECK-NEXT: vdup.8 q3, r0 986; CHECK-NEXT: vcmp.u8 cs, q3, q0 987; CHECK-NEXT: vpsel q0, q1, q2 988; CHECK-NEXT: bx lr 989entry: 990 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 991 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 992 %c = icmp uge <16 x i8> %sp, %src 993 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 994 ret <16 x i8> %s 995} 996 997define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ult_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 998; CHECK-LABEL: vcmp_r_ult_v16i8: 999; CHECK: @ %bb.0: @ %entry 1000; CHECK-NEXT: vcmp.u8 hi, q0, r0 1001; CHECK-NEXT: vpsel q0, q1, q2 1002; CHECK-NEXT: bx lr 1003entry: 1004 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 1005 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 1006 %c = icmp ult <16 x i8> %sp, %src 1007 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 1008 ret <16 x i8> %s 1009} 1010 1011define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ule_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 1012; CHECK-LABEL: vcmp_r_ule_v16i8: 1013; CHECK: @ %bb.0: @ %entry 1014; CHECK-NEXT: vcmp.u8 cs, q0, r0 1015; CHECK-NEXT: vpsel q0, q1, q2 1016; CHECK-NEXT: bx lr 1017entry: 1018 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 1019 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 1020 %c = icmp ule <16 x i8> %sp, %src 1021 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b 1022 ret <16 x i8> %s 1023} 1024 1025 1026define arm_aapcs_vfpcc <2 x i64> @vcmp_r_eq_v2i64(<2 x i64> %src, i64 %src2, <2 x i64> %a, <2 x i64> %b) { 1027; CHECK-LABEL: vcmp_r_eq_v2i64: 1028; CHECK: @ %bb.0: @ %entry 1029; CHECK-NEXT: vmov r2, s1 1030; CHECK-NEXT: vmov r3, s0 1031; CHECK-NEXT: eors r2, r1 1032; CHECK-NEXT: eors r3, r0 1033; CHECK-NEXT: orrs r2, r3 1034; CHECK-NEXT: cset r2, eq 1035; CHECK-NEXT: tst.w r2, #1 1036; CHECK-NEXT: csetm r2, ne 1037; CHECK-NEXT: vmov.32 q3[0], r2 1038; CHECK-NEXT: vmov.32 q3[1], r2 1039; CHECK-NEXT: vmov r2, s3 1040; CHECK-NEXT: eors r1, r2 1041; CHECK-NEXT: vmov r2, s2 1042; CHECK-NEXT: eors r0, r2 1043; CHECK-NEXT: orrs r0, r1 1044; CHECK-NEXT: cset r0, eq 1045; CHECK-NEXT: tst.w r0, #1 1046; CHECK-NEXT: csetm r0, ne 1047; CHECK-NEXT: vmov.32 q3[2], r0 1048; CHECK-NEXT: vmov.32 q3[3], r0 1049; CHECK-NEXT: vbic q0, q2, q3 1050; CHECK-NEXT: vand q1, q1, q3 1051; CHECK-NEXT: vorr q0, q1, q0 1052; CHECK-NEXT: bx lr 1053entry: 1054 %i = insertelement <2 x i64> undef, i64 %src2, i32 0 1055 %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer 1056 %c = icmp eq <2 x i64> %sp, %src 1057 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b 1058 ret <2 x i64> %s 1059} 1060 1061define arm_aapcs_vfpcc <2 x i32> @vcmp_r_eq_v2i32(<2 x i64> %src, i64 %src2, <2 x i32> %a, <2 x i32> %b) { 1062; CHECK-LABEL: vcmp_r_eq_v2i32: 1063; CHECK: @ %bb.0: @ %entry 1064; CHECK-NEXT: vmov r2, s1 1065; CHECK-NEXT: vmov r3, s0 1066; CHECK-NEXT: eors r2, r1 1067; CHECK-NEXT: eors r3, r0 1068; CHECK-NEXT: orrs r2, r3 1069; CHECK-NEXT: cset r2, eq 1070; CHECK-NEXT: tst.w r2, #1 1071; CHECK-NEXT: csetm r2, ne 1072; CHECK-NEXT: vmov.32 q3[0], r2 1073; CHECK-NEXT: vmov.32 q3[1], r2 1074; CHECK-NEXT: vmov r2, s3 1075; CHECK-NEXT: eors r1, r2 1076; CHECK-NEXT: vmov r2, s2 1077; CHECK-NEXT: eors r0, r2 1078; CHECK-NEXT: orrs r0, r1 1079; CHECK-NEXT: cset r0, eq 1080; CHECK-NEXT: tst.w r0, #1 1081; CHECK-NEXT: csetm r0, ne 1082; CHECK-NEXT: vmov.32 q3[2], r0 1083; CHECK-NEXT: vmov.32 q3[3], r0 1084; CHECK-NEXT: vbic q0, q2, q3 1085; CHECK-NEXT: vand q1, q1, q3 1086; CHECK-NEXT: vorr q0, q1, q0 1087; CHECK-NEXT: bx lr 1088entry: 1089 %i = insertelement <2 x i64> undef, i64 %src2, i32 0 1090 %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer 1091 %c = icmp eq <2 x i64> %sp, %src 1092 %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b 1093 ret <2 x i32> %s 1094} 1095 1096define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) { 1097; CHECK-LABEL: vcmp_r_multi_v2i32: 1098; CHECK: @ %bb.0: 1099; CHECK-NEXT: .save {r7, lr} 1100; CHECK-NEXT: push {r7, lr} 1101; CHECK-NEXT: .vsave {d8, d9, d10, d11} 1102; CHECK-NEXT: vpush {d8, d9, d10, d11} 1103; CHECK-NEXT: vmov r0, s1 1104; CHECK-NEXT: movs r3, #0 1105; CHECK-NEXT: vmov r1, s0 1106; CHECK-NEXT: vmov r2, s8 1107; CHECK-NEXT: orrs r0, r1 1108; CHECK-NEXT: vmov r1, s2 1109; CHECK-NEXT: cset r0, eq 1110; CHECK-NEXT: tst.w r0, #1 1111; CHECK-NEXT: csetm r0, ne 1112; CHECK-NEXT: vmov.32 q3[0], r0 1113; CHECK-NEXT: vmov.32 q3[1], r0 1114; CHECK-NEXT: vmov r0, s3 1115; CHECK-NEXT: orrs r0, r1 1116; CHECK-NEXT: cset r0, eq 1117; CHECK-NEXT: tst.w r0, #1 1118; CHECK-NEXT: csetm r0, ne 1119; CHECK-NEXT: vmov.32 q3[2], r0 1120; CHECK-NEXT: vmov.32 q3[3], r0 1121; CHECK-NEXT: vbic q0, q2, q3 1122; CHECK-NEXT: vmov lr, s0 1123; CHECK-NEXT: subs.w r1, lr, r2 1124; CHECK-NEXT: asr.w r12, lr, #31 1125; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31 1126; CHECK-NEXT: mov.w r1, #0 1127; CHECK-NEXT: vmov r2, s10 1128; CHECK-NEXT: it lt 1129; CHECK-NEXT: movlt r1, #1 1130; CHECK-NEXT: cmp r1, #0 1131; CHECK-NEXT: csetm r1, ne 1132; CHECK-NEXT: vmov.32 q3[0], r1 1133; CHECK-NEXT: vmov.32 q3[1], r1 1134; CHECK-NEXT: vmov r1, s2 1135; CHECK-NEXT: subs r0, r1, r2 1136; CHECK-NEXT: asr.w r12, r1, #31 1137; CHECK-NEXT: sbcs.w r0, r12, r2, asr #31 1138; CHECK-NEXT: it lt 1139; CHECK-NEXT: movlt r3, #1 1140; CHECK-NEXT: cmp r3, #0 1141; CHECK-NEXT: csetm r0, ne 1142; CHECK-NEXT: cmp.w lr, #0 1143; CHECK-NEXT: vmov.32 q3[2], r0 1144; CHECK-NEXT: vmov.32 q3[3], r0 1145; CHECK-NEXT: cset r0, ne 1146; CHECK-NEXT: tst.w r0, #1 1147; CHECK-NEXT: csetm r0, ne 1148; CHECK-NEXT: cmp r1, #0 1149; CHECK-NEXT: vmov.32 q4[0], r0 1150; CHECK-NEXT: vmov.32 q4[1], r0 1151; CHECK-NEXT: cset r0, ne 1152; CHECK-NEXT: tst.w r0, #1 1153; CHECK-NEXT: csetm r0, ne 1154; CHECK-NEXT: vmov.32 q4[2], r0 1155; CHECK-NEXT: vmov.32 q4[3], r0 1156; CHECK-NEXT: vmov r0, s4 1157; CHECK-NEXT: cmp r0, #0 1158; CHECK-NEXT: cset r0, ne 1159; CHECK-NEXT: tst.w r0, #1 1160; CHECK-NEXT: csetm r0, ne 1161; CHECK-NEXT: vmov.32 q5[0], r0 1162; CHECK-NEXT: vmov.32 q5[1], r0 1163; CHECK-NEXT: vmov r0, s6 1164; CHECK-NEXT: cmp r0, #0 1165; CHECK-NEXT: cset r0, ne 1166; CHECK-NEXT: tst.w r0, #1 1167; CHECK-NEXT: csetm r0, ne 1168; CHECK-NEXT: vmov.32 q5[2], r0 1169; CHECK-NEXT: vmov.32 q5[3], r0 1170; CHECK-NEXT: vand q1, q5, q4 1171; CHECK-NEXT: vand q1, q3, q1 1172; CHECK-NEXT: vbic q0, q0, q1 1173; CHECK-NEXT: vand q1, q2, q1 1174; CHECK-NEXT: vorr q0, q1, q0 1175; CHECK-NEXT: vpop {d8, d9, d10, d11} 1176; CHECK-NEXT: pop {r7, pc} 1177 %a4 = icmp eq <2 x i64> %a, zeroinitializer 1178 %a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c 1179 %a6 = icmp ne <2 x i32> %b, zeroinitializer 1180 %a7 = icmp slt <2 x i32> %a5, %c 1181 %a8 = icmp ne <2 x i32> %a5, zeroinitializer 1182 %a9 = and <2 x i1> %a6, %a8 1183 %a10 = and <2 x i1> %a7, %a9 1184 %a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5 1185 ret <2 x i32> %a11 1186} 1187