1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve --verify-machineinstrs %s -o - | FileCheck %s 3 4define void @vctp8(i32 %arg, <16 x i8> *%in, <16 x i8>* %out) { 5; CHECK-LABEL: vctp8: 6; CHECK: @ %bb.0: 7; CHECK-NEXT: vmov.i32 q0, #0x0 8; CHECK-NEXT: vctp.8 r0 9; CHECK-NEXT: vldrw.u32 q1, [r1] 10; CHECK-NEXT: vpst 11; CHECK-NEXT: vmovt q0, q1 12; CHECK-NEXT: vstrw.32 q0, [r2] 13; CHECK-NEXT: bx lr 14 %pred = call <16 x i1> @llvm.arm.mve.vctp8(i32 %arg) 15 %ld = load <16 x i8>, <16 x i8>* %in 16 %res = select <16 x i1> %pred, <16 x i8> %ld, <16 x i8> zeroinitializer 17 store <16 x i8> %res, <16 x i8>* %out 18 ret void 19} 20 21define void @vctp16(i32 %arg, <8 x i16> *%in, <8 x i16>* %out) { 22; CHECK-LABEL: vctp16: 23; CHECK: @ %bb.0: 24; CHECK-NEXT: vmov.i32 q0, #0x0 25; CHECK-NEXT: vctp.16 r0 26; CHECK-NEXT: vldrw.u32 q1, [r1] 27; CHECK-NEXT: vpst 28; CHECK-NEXT: vmovt q0, q1 29; CHECK-NEXT: vstrw.32 q0, [r2] 30; CHECK-NEXT: bx lr 31 %pred = call <8 x i1> @llvm.arm.mve.vctp16(i32 %arg) 32 %ld = load <8 x i16>, <8 x i16>* %in 33 %res = select <8 x i1> %pred, <8 x i16> %ld, <8 x i16> zeroinitializer 34 store <8 x i16> %res, <8 x i16>* %out 35 ret void 36} 37 38define void @vctp32(i32 %arg, <4 x i32> *%in, <4 x i32>* %out) { 39; CHECK-LABEL: vctp32: 40; CHECK: @ %bb.0: 41; CHECK-NEXT: vmov.i32 q0, #0x0 42; CHECK-NEXT: vctp.32 r0 43; CHECK-NEXT: vldrw.u32 q1, [r1] 44; CHECK-NEXT: vpst 45; CHECK-NEXT: vmovt q0, q1 46; CHECK-NEXT: vstrw.32 q0, [r2] 47; CHECK-NEXT: bx lr 48 %pred = call <4 x i1> @llvm.arm.mve.vctp32(i32 %arg) 49 %ld = load <4 x i32>, <4 x i32>* %in 50 %res = select <4 x i1> %pred, <4 x i32> %ld, <4 x i32> zeroinitializer 51 store <4 x i32> %res, <4 x i32>* %out 52 ret void 53} 54 55declare <16 x i1> @llvm.arm.mve.vctp8(i32) 56declare <8 x i1> @llvm.arm.mve.vctp16(i32) 57declare <4 x i1> @llvm.arm.mve.vctp32(i32) 58