1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s 3 4; i32 5 6define <8 x i32> *@vld2_v4i32(<8 x i32> *%src, <4 x i32> *%dst) { 7; CHECK-LABEL: vld2_v4i32: 8; CHECK: @ %bb.0: @ %entry 9; CHECK-NEXT: vld20.32 {q0, q1}, [r0] 10; CHECK-NEXT: vld21.32 {q0, q1}, [r0]! 11; CHECK-NEXT: vadd.i32 q0, q0, q1 12; CHECK-NEXT: vstrw.32 q0, [r1] 13; CHECK-NEXT: bx lr 14entry: 15 %l1 = load <8 x i32>, <8 x i32>* %src, align 4 16 %s1 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> 17 %s2 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> 18 %a = add <4 x i32> %s1, %s2 19 store <4 x i32> %a, <4 x i32> *%dst 20 %ret = getelementptr inbounds <8 x i32>, <8 x i32>* %src, i32 1 21 ret <8 x i32> *%ret 22} 23 24; i16 25 26define <16 x i16> *@vld2_v8i16(<16 x i16> *%src, <8 x i16> *%dst) { 27; CHECK-LABEL: vld2_v8i16: 28; CHECK: @ %bb.0: @ %entry 29; CHECK-NEXT: vld20.16 {q0, q1}, [r0] 30; CHECK-NEXT: vld21.16 {q0, q1}, [r0]! 31; CHECK-NEXT: vadd.i16 q0, q0, q1 32; CHECK-NEXT: vstrw.32 q0, [r1] 33; CHECK-NEXT: bx lr 34entry: 35 %l1 = load <16 x i16>, <16 x i16>* %src, align 4 36 %s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> 37 %s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> 38 %a = add <8 x i16> %s1, %s2 39 store <8 x i16> %a, <8 x i16> *%dst 40 %ret = getelementptr inbounds <16 x i16>, <16 x i16>* %src, i32 1 41 ret <16 x i16> *%ret 42} 43 44; i8 45 46define <32 x i8> *@vld2_v16i8(<32 x i8> *%src, <16 x i8> *%dst) { 47; CHECK-LABEL: vld2_v16i8: 48; CHECK: @ %bb.0: @ %entry 49; CHECK-NEXT: vld20.8 {q0, q1}, [r0] 50; CHECK-NEXT: vld21.8 {q0, q1}, [r0]! 51; CHECK-NEXT: vadd.i8 q0, q0, q1 52; CHECK-NEXT: vstrw.32 q0, [r1] 53; CHECK-NEXT: bx lr 54entry: 55 %l1 = load <32 x i8>, <32 x i8>* %src, align 4 56 %s1 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> 57 %s2 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> 58 %a = add <16 x i8> %s1, %s2 59 store <16 x i8> %a, <16 x i8> *%dst 60 %ret = getelementptr inbounds <32 x i8>, <32 x i8>* %src, i32 1 61 ret <32 x i8> *%ret 62} 63 64; i64 65 66define <4 x i64> *@vld2_v2i64(<4 x i64> *%src, <2 x i64> *%dst) { 67; CHECK-LABEL: vld2_v2i64: 68; CHECK: @ %bb.0: @ %entry 69; CHECK-NEXT: .save {r4, r5, r6, lr} 70; CHECK-NEXT: push {r4, r5, r6, lr} 71; CHECK-NEXT: vldrw.u32 q2, [r0, #16] 72; CHECK-NEXT: vldrw.u32 q0, [r0], #32 73; CHECK-NEXT: vmov.f64 d2, d1 74; CHECK-NEXT: vmov.f32 s5, s3 75; CHECK-NEXT: vmov.f32 s6, s10 76; CHECK-NEXT: vmov.f32 s2, s8 77; CHECK-NEXT: vmov.f32 s7, s11 78; CHECK-NEXT: vmov.f32 s3, s9 79; CHECK-NEXT: vmov r2, s6 80; CHECK-NEXT: vmov r3, s2 81; CHECK-NEXT: vmov r4, s4 82; CHECK-NEXT: vmov r5, s0 83; CHECK-NEXT: vmov r12, s7 84; CHECK-NEXT: vmov lr, s3 85; CHECK-NEXT: adds r6, r3, r2 86; CHECK-NEXT: vmov r3, s5 87; CHECK-NEXT: vmov r2, s1 88; CHECK-NEXT: adc.w r12, r12, lr 89; CHECK-NEXT: adds r5, r5, r4 90; CHECK-NEXT: vmov.32 q0[0], r5 91; CHECK-NEXT: adcs r2, r3 92; CHECK-NEXT: vmov.32 q0[1], r2 93; CHECK-NEXT: vmov.32 q0[2], r6 94; CHECK-NEXT: vmov.32 q0[3], r12 95; CHECK-NEXT: vstrw.32 q0, [r1] 96; CHECK-NEXT: pop {r4, r5, r6, pc} 97entry: 98 %l1 = load <4 x i64>, <4 x i64>* %src, align 4 99 %s1 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 0, i32 2> 100 %s2 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 1, i32 3> 101 %a = add <2 x i64> %s1, %s2 102 store <2 x i64> %a, <2 x i64> *%dst 103 %ret = getelementptr inbounds <4 x i64>, <4 x i64>* %src, i32 1 104 ret <4 x i64> *%ret 105} 106 107; f32 108 109define <8 x float> *@vld2_v4f32(<8 x float> *%src, <4 x float> *%dst) { 110; CHECK-LABEL: vld2_v4f32: 111; CHECK: @ %bb.0: @ %entry 112; CHECK-NEXT: vld20.32 {q0, q1}, [r0] 113; CHECK-NEXT: vld21.32 {q0, q1}, [r0]! 114; CHECK-NEXT: vadd.f32 q0, q0, q1 115; CHECK-NEXT: vstrw.32 q0, [r1] 116; CHECK-NEXT: bx lr 117entry: 118 %l1 = load <8 x float>, <8 x float>* %src, align 4 119 %s1 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> 120 %s2 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> 121 %a = fadd <4 x float> %s1, %s2 122 store <4 x float> %a, <4 x float> *%dst 123 %ret = getelementptr inbounds <8 x float>, <8 x float>* %src, i32 1 124 ret <8 x float> *%ret 125} 126 127; f16 128 129define <16 x half> *@vld2_v8f16(<16 x half> *%src, <8 x half> *%dst) { 130; CHECK-LABEL: vld2_v8f16: 131; CHECK: @ %bb.0: @ %entry 132; CHECK-NEXT: vld20.16 {q0, q1}, [r0] 133; CHECK-NEXT: vld21.16 {q0, q1}, [r0]! 134; CHECK-NEXT: vadd.f16 q0, q0, q1 135; CHECK-NEXT: vstrw.32 q0, [r1] 136; CHECK-NEXT: bx lr 137entry: 138 %l1 = load <16 x half>, <16 x half>* %src, align 4 139 %s1 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> 140 %s2 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> 141 %a = fadd <8 x half> %s1, %s2 142 store <8 x half> %a, <8 x half> *%dst 143 %ret = getelementptr inbounds <16 x half>, <16 x half>* %src, i32 1 144 ret <16 x half> *%ret 145} 146 147; f64 148 149define <4 x double> *@vld2_v2f64(<4 x double> *%src, <2 x double> *%dst) { 150; CHECK-LABEL: vld2_v2f64: 151; CHECK: @ %bb.0: @ %entry 152; CHECK-NEXT: vldrw.u32 q0, [r0, #16] 153; CHECK-NEXT: vldrw.u32 q1, [r0], #32 154; CHECK-NEXT: vadd.f64 d1, d0, d1 155; CHECK-NEXT: vadd.f64 d0, d2, d3 156; CHECK-NEXT: vstrw.32 q0, [r1] 157; CHECK-NEXT: bx lr 158entry: 159 %l1 = load <4 x double>, <4 x double>* %src, align 4 160 %s1 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 0, i32 2> 161 %s2 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 1, i32 3> 162 %a = fadd <2 x double> %s1, %s2 163 store <2 x double> %a, <2 x double> *%dst 164 %ret = getelementptr inbounds <4 x double>, <4 x double>* %src, i32 1 165 ret <4 x double> *%ret 166} 167