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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s
3
4; i32
5
6define <16 x i32> *@vld4_v4i32(<16 x i32> *%src, <4 x i32> *%dst) {
7; CHECK-LABEL: vld4_v4i32:
8; CHECK:       @ %bb.0: @ %entry
9; CHECK-NEXT:    .vsave {d8, d9}
10; CHECK-NEXT:    vpush {d8, d9}
11; CHECK-NEXT:    vld40.32 {q0, q1, q2, q3}, [r0]
12; CHECK-NEXT:    vld41.32 {q0, q1, q2, q3}, [r0]
13; CHECK-NEXT:    vld42.32 {q0, q1, q2, q3}, [r0]
14; CHECK-NEXT:    vld43.32 {q0, q1, q2, q3}, [r0]!
15; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
16; CHECK-NEXT:    vadd.i32 q4, q2, q3
17; CHECK-NEXT:    vadd.i32 q0, q0, q1
18; CHECK-NEXT:    vadd.i32 q0, q0, q4
19; CHECK-NEXT:    vstrw.32 q0, [r1]
20; CHECK-NEXT:    vpop {d8, d9}
21; CHECK-NEXT:    bx lr
22entry:
23  %l1 = load <16 x i32>, <16 x i32>* %src, align 4
24  %s1 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
25  %s2 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
26  %s3 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
27  %s4 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
28  %a1 = add <4 x i32> %s1, %s2
29  %a2 = add <4 x i32> %s3, %s4
30  %a3 = add <4 x i32> %a1, %a2
31  store <4 x i32> %a3, <4 x i32> *%dst
32  %ret = getelementptr inbounds <16 x i32>, <16 x i32>* %src, i32 1
33  ret <16 x i32> *%ret
34}
35
36; i16
37
38define <32 x i16> *@vld4_v8i16(<32 x i16> *%src, <8 x i16> *%dst) {
39; CHECK-LABEL: vld4_v8i16:
40; CHECK:       @ %bb.0: @ %entry
41; CHECK-NEXT:    .vsave {d8, d9}
42; CHECK-NEXT:    vpush {d8, d9}
43; CHECK-NEXT:    vld40.16 {q0, q1, q2, q3}, [r0]
44; CHECK-NEXT:    vld41.16 {q0, q1, q2, q3}, [r0]
45; CHECK-NEXT:    vld42.16 {q0, q1, q2, q3}, [r0]
46; CHECK-NEXT:    vld43.16 {q0, q1, q2, q3}, [r0]!
47; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
48; CHECK-NEXT:    vadd.i16 q4, q2, q3
49; CHECK-NEXT:    vadd.i16 q0, q0, q1
50; CHECK-NEXT:    vadd.i16 q0, q0, q4
51; CHECK-NEXT:    vstrw.32 q0, [r1]
52; CHECK-NEXT:    vpop {d8, d9}
53; CHECK-NEXT:    bx lr
54entry:
55  %l1 = load <32 x i16>, <32 x i16>* %src, align 4
56  %s1 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
57  %s2 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
58  %s3 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
59  %s4 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
60  %a1 = add <8 x i16> %s1, %s2
61  %a2 = add <8 x i16> %s3, %s4
62  %a3 = add <8 x i16> %a1, %a2
63  store <8 x i16> %a3, <8 x i16> *%dst
64  %ret = getelementptr inbounds <32 x i16>, <32 x i16>* %src, i32 1
65  ret <32 x i16> *%ret
66}
67
68; i8
69
70define <64 x i8> *@vld4_v16i8(<64 x i8> *%src, <16 x i8> *%dst) {
71; CHECK-LABEL: vld4_v16i8:
72; CHECK:       @ %bb.0: @ %entry
73; CHECK-NEXT:    .vsave {d8, d9}
74; CHECK-NEXT:    vpush {d8, d9}
75; CHECK-NEXT:    vld40.8 {q0, q1, q2, q3}, [r0]
76; CHECK-NEXT:    vld41.8 {q0, q1, q2, q3}, [r0]
77; CHECK-NEXT:    vld42.8 {q0, q1, q2, q3}, [r0]
78; CHECK-NEXT:    vld43.8 {q0, q1, q2, q3}, [r0]!
79; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
80; CHECK-NEXT:    vadd.i8 q4, q2, q3
81; CHECK-NEXT:    vadd.i8 q0, q0, q1
82; CHECK-NEXT:    vadd.i8 q0, q0, q4
83; CHECK-NEXT:    vstrw.32 q0, [r1]
84; CHECK-NEXT:    vpop {d8, d9}
85; CHECK-NEXT:    bx lr
86entry:
87  %l1 = load <64 x i8>, <64 x i8>* %src, align 4
88  %s1 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>
89  %s2 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61>
90  %s3 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62>
91  %s4 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63>
92  %a1 = add <16 x i8> %s1, %s2
93  %a2 = add <16 x i8> %s3, %s4
94  %a3 = add <16 x i8> %a1, %a2
95  store <16 x i8> %a3, <16 x i8> *%dst
96  %ret = getelementptr inbounds <64 x i8>, <64 x i8>* %src, i32 1
97  ret <64 x i8> *%ret
98}
99
100; i64
101
102define <8 x i64> *@vld4_v2i64(<8 x i64> *%src, <2 x i64> *%dst) {
103; CHECK-LABEL: vld4_v2i64:
104; CHECK:       @ %bb.0: @ %entry
105; CHECK-NEXT:    .save {r4, r5, r6, r7, lr}
106; CHECK-NEXT:    push {r4, r5, r6, r7, lr}
107; CHECK-NEXT:    .pad #4
108; CHECK-NEXT:    sub sp, #4
109; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
110; CHECK-NEXT:    vpush {d8, d9, d10, d11}
111; CHECK-NEXT:    vldrw.u32 q2, [r0, #32]
112; CHECK-NEXT:    vldrw.u32 q0, [r0], #64
113; CHECK-NEXT:    vldrw.u32 q3, [r0, #-48]
114; CHECK-NEXT:    vldrw.u32 q5, [r0, #-16]
115; CHECK-NEXT:    vmov.f64 d2, d1
116; CHECK-NEXT:    vmov.f64 d8, d7
117; CHECK-NEXT:    vmov.f32 s17, s15
118; CHECK-NEXT:    vmov.f32 s18, s22
119; CHECK-NEXT:    vmov.f32 s14, s20
120; CHECK-NEXT:    vmov.f32 s19, s23
121; CHECK-NEXT:    vmov.f32 s15, s21
122; CHECK-NEXT:    vmov r2, s18
123; CHECK-NEXT:    vmov r3, s14
124; CHECK-NEXT:    vmov.f32 s5, s3
125; CHECK-NEXT:    vmov.f32 s6, s10
126; CHECK-NEXT:    vmov.f32 s2, s8
127; CHECK-NEXT:    vmov.f32 s3, s9
128; CHECK-NEXT:    vmov.f32 s7, s11
129; CHECK-NEXT:    vmov r12, s19
130; CHECK-NEXT:    vmov lr, s15
131; CHECK-NEXT:    vmov r4, s6
132; CHECK-NEXT:    vmov r5, s2
133; CHECK-NEXT:    vmov r7, s0
134; CHECK-NEXT:    adds r6, r3, r2
135; CHECK-NEXT:    vmov r2, s7
136; CHECK-NEXT:    vmov r3, s3
137; CHECK-NEXT:    adc.w r12, r12, lr
138; CHECK-NEXT:    adds r5, r5, r4
139; CHECK-NEXT:    vmov r4, s16
140; CHECK-NEXT:    adcs r2, r3
141; CHECK-NEXT:    adds.w lr, r5, r6
142; CHECK-NEXT:    adc.w r12, r12, r2
143; CHECK-NEXT:    vmov r2, s12
144; CHECK-NEXT:    vmov r6, s17
145; CHECK-NEXT:    vmov r5, s13
146; CHECK-NEXT:    vmov r3, s4
147; CHECK-NEXT:    adds r2, r2, r4
148; CHECK-NEXT:    vmov r4, s1
149; CHECK-NEXT:    adcs r6, r5
150; CHECK-NEXT:    vmov r5, s5
151; CHECK-NEXT:    adds r3, r3, r7
152; CHECK-NEXT:    adcs r4, r5
153; CHECK-NEXT:    adds r2, r2, r3
154; CHECK-NEXT:    adc.w r3, r4, r6
155; CHECK-NEXT:    vmov.32 q0[0], r2
156; CHECK-NEXT:    vmov.32 q0[1], r3
157; CHECK-NEXT:    vmov.32 q0[2], lr
158; CHECK-NEXT:    vmov.32 q0[3], r12
159; CHECK-NEXT:    vstrw.32 q0, [r1]
160; CHECK-NEXT:    vpop {d8, d9, d10, d11}
161; CHECK-NEXT:    add sp, #4
162; CHECK-NEXT:    pop {r4, r5, r6, r7, pc}
163entry:
164  %l1 = load <8 x i64>, <8 x i64>* %src, align 4
165  %s1 = shufflevector <8 x i64> %l1, <8 x i64> undef, <2 x i32> <i32 0, i32 4>
166  %s2 = shufflevector <8 x i64> %l1, <8 x i64> undef, <2 x i32> <i32 1, i32 5>
167  %s3 = shufflevector <8 x i64> %l1, <8 x i64> undef, <2 x i32> <i32 2, i32 6>
168  %s4 = shufflevector <8 x i64> %l1, <8 x i64> undef, <2 x i32> <i32 3, i32 7>
169  %a1 = add <2 x i64> %s1, %s2
170  %a2 = add <2 x i64> %s3, %s4
171  %a3 = add <2 x i64> %a1, %a2
172  store <2 x i64> %a3, <2 x i64> *%dst
173  %ret = getelementptr inbounds <8 x i64>, <8 x i64>* %src, i32 1
174  ret <8 x i64> *%ret
175}
176
177; f32
178
179define <16 x float> *@vld4_v4f32(<16 x float> *%src, <4 x float> *%dst) {
180; CHECK-LABEL: vld4_v4f32:
181; CHECK:       @ %bb.0: @ %entry
182; CHECK-NEXT:    .vsave {d8, d9}
183; CHECK-NEXT:    vpush {d8, d9}
184; CHECK-NEXT:    vld40.32 {q0, q1, q2, q3}, [r0]
185; CHECK-NEXT:    vld41.32 {q0, q1, q2, q3}, [r0]
186; CHECK-NEXT:    vld42.32 {q0, q1, q2, q3}, [r0]
187; CHECK-NEXT:    vld43.32 {q0, q1, q2, q3}, [r0]!
188; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
189; CHECK-NEXT:    vadd.f32 q4, q2, q3
190; CHECK-NEXT:    vadd.f32 q0, q0, q1
191; CHECK-NEXT:    vadd.f32 q0, q0, q4
192; CHECK-NEXT:    vstrw.32 q0, [r1]
193; CHECK-NEXT:    vpop {d8, d9}
194; CHECK-NEXT:    bx lr
195entry:
196  %l1 = load <16 x float>, <16 x float>* %src, align 4
197  %s1 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
198  %s2 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
199  %s3 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
200  %s4 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
201  %a1 = fadd <4 x float> %s1, %s2
202  %a2 = fadd <4 x float> %s3, %s4
203  %a3 = fadd <4 x float> %a1, %a2
204  store <4 x float> %a3, <4 x float> *%dst
205  %ret = getelementptr inbounds <16 x float>, <16 x float>* %src, i32 1
206  ret <16 x float> *%ret
207}
208
209; f16
210
211define <32 x half> *@vld4_v8f16(<32 x half> *%src, <8 x half> *%dst) {
212; CHECK-LABEL: vld4_v8f16:
213; CHECK:       @ %bb.0: @ %entry
214; CHECK-NEXT:    .vsave {d8, d9}
215; CHECK-NEXT:    vpush {d8, d9}
216; CHECK-NEXT:    vld40.16 {q0, q1, q2, q3}, [r0]
217; CHECK-NEXT:    vld41.16 {q0, q1, q2, q3}, [r0]
218; CHECK-NEXT:    vld42.16 {q0, q1, q2, q3}, [r0]
219; CHECK-NEXT:    vld43.16 {q0, q1, q2, q3}, [r0]!
220; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
221; CHECK-NEXT:    vadd.f16 q4, q2, q3
222; CHECK-NEXT:    vadd.f16 q0, q0, q1
223; CHECK-NEXT:    vadd.f16 q0, q0, q4
224; CHECK-NEXT:    vstrw.32 q0, [r1]
225; CHECK-NEXT:    vpop {d8, d9}
226; CHECK-NEXT:    bx lr
227entry:
228  %l1 = load <32 x half>, <32 x half>* %src, align 4
229  %s1 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
230  %s2 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
231  %s3 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
232  %s4 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
233  %a1 = fadd <8 x half> %s1, %s2
234  %a2 = fadd <8 x half> %s3, %s4
235  %a3 = fadd <8 x half> %a1, %a2
236  store <8 x half> %a3, <8 x half> *%dst
237  %ret = getelementptr inbounds <32 x half>, <32 x half>* %src, i32 1
238  ret <32 x half> *%ret
239}
240
241; f64
242
243define <8 x double> *@vld4_v2f64(<8 x double> *%src, <2 x double> *%dst) {
244; CHECK-LABEL: vld4_v2f64:
245; CHECK:       @ %bb.0: @ %entry
246; CHECK-NEXT:    vldrw.u32 q0, [r0, #48]
247; CHECK-NEXT:    vldrw.u32 q1, [r0, #32]
248; CHECK-NEXT:    vadd.f64 d0, d0, d1
249; CHECK-NEXT:    vadd.f64 d1, d2, d3
250; CHECK-NEXT:    vldrw.u32 q1, [r0, #16]
251; CHECK-NEXT:    vldrw.u32 q2, [r0], #64
252; CHECK-NEXT:    vadd.f64 d2, d2, d3
253; CHECK-NEXT:    vadd.f64 d3, d4, d5
254; CHECK-NEXT:    vadd.f64 d1, d1, d0
255; CHECK-NEXT:    vadd.f64 d0, d3, d2
256; CHECK-NEXT:    vstrw.32 q0, [r1]
257; CHECK-NEXT:    bx lr
258entry:
259  %l1 = load <8 x double>, <8 x double>* %src, align 4
260  %s1 = shufflevector <8 x double> %l1, <8 x double> undef, <2 x i32> <i32 0, i32 4>
261  %s2 = shufflevector <8 x double> %l1, <8 x double> undef, <2 x i32> <i32 1, i32 5>
262  %s3 = shufflevector <8 x double> %l1, <8 x double> undef, <2 x i32> <i32 2, i32 6>
263  %s4 = shufflevector <8 x double> %l1, <8 x double> undef, <2 x i32> <i32 3, i32 7>
264  %a1 = fadd <2 x double> %s1, %s2
265  %a2 = fadd <2 x double> %s3, %s4
266  %a3 = fadd <2 x double> %a1, %a2
267  store <2 x double> %a3, <2 x double> *%dst
268  %ret = getelementptr inbounds <8 x double>, <8 x double>* %src, i32 1
269  ret <8 x double> *%ret
270}
271