1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s 3 4define arm_aapcs_vfpcc void @vmovn32_trunc1(<4 x i32> %src1, <4 x i32> %src2, <8 x i16> *%dest) { 5; CHECK-LABEL: vmovn32_trunc1: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vmovnt.i32 q0, q1 8; CHECK-NEXT: vstrw.32 q0, [r0] 9; CHECK-NEXT: bx lr 10entry: 11 %strided.vec = shufflevector <4 x i32> %src1, <4 x i32> %src2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> 12 %out = trunc <8 x i32> %strided.vec to <8 x i16> 13 store <8 x i16> %out, <8 x i16> *%dest, align 8 14 ret void 15} 16 17define arm_aapcs_vfpcc void @vmovn32_trunc2(<4 x i32> %src1, <4 x i32> %src2, <8 x i16> *%dest) { 18; CHECK-LABEL: vmovn32_trunc2: 19; CHECK: @ %bb.0: @ %entry 20; CHECK-NEXT: vmovnt.i32 q1, q0 21; CHECK-NEXT: vstrw.32 q1, [r0] 22; CHECK-NEXT: bx lr 23entry: 24 %strided.vec = shufflevector <4 x i32> %src1, <4 x i32> %src2, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3> 25 %out = trunc <8 x i32> %strided.vec to <8 x i16> 26 store <8 x i16> %out, <8 x i16> *%dest, align 8 27 ret void 28} 29 30define arm_aapcs_vfpcc void @vmovn16_trunc1(<8 x i16> %src1, <8 x i16> %src2, <16 x i8> *%dest) { 31; CHECK-LABEL: vmovn16_trunc1: 32; CHECK: @ %bb.0: @ %entry 33; CHECK-NEXT: vmovnt.i16 q0, q1 34; CHECK-NEXT: vstrw.32 q0, [r0] 35; CHECK-NEXT: bx lr 36entry: 37 %strided.vec = shufflevector <8 x i16> %src1, <8 x i16> %src2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> 38 %out = trunc <16 x i16> %strided.vec to <16 x i8> 39 store <16 x i8> %out, <16 x i8> *%dest, align 8 40 ret void 41} 42 43define arm_aapcs_vfpcc void @vmovn16_trunc2(<8 x i16> %src1, <8 x i16> %src2, <16 x i8> *%dest) { 44; CHECK-LABEL: vmovn16_trunc2: 45; CHECK: @ %bb.0: @ %entry 46; CHECK-NEXT: vmovnt.i16 q1, q0 47; CHECK-NEXT: vstrw.32 q1, [r0] 48; CHECK-NEXT: bx lr 49entry: 50 %strided.vec = shufflevector <8 x i16> %src1, <8 x i16> %src2, <16 x i32> <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3, i32 12, i32 4, i32 13, i32 5, i32 14, i32 6, i32 15, i32 7> 51 %out = trunc <16 x i16> %strided.vec to <16 x i8> 52 store <16 x i8> %out, <16 x i8> *%dest, align 8 53 ret void 54} 55 56 57define arm_aapcs_vfpcc void @vmovn64_t1(<2 x i64> %src1, <2 x i64> %src2, <2 x i64> *%dest) { 58; CHECK-LABEL: vmovn64_t1: 59; CHECK: @ %bb.0: @ %entry 60; CHECK-NEXT: vmov.f32 s2, s4 61; CHECK-NEXT: vmov.f32 s3, s5 62; CHECK-NEXT: vstrw.32 q0, [r0] 63; CHECK-NEXT: bx lr 64entry: 65 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 0, i32 2> 66 store <2 x i64> %out, <2 x i64> *%dest, align 8 67 ret void 68} 69 70define arm_aapcs_vfpcc void @vmovn64_t2(<2 x i64> %src1, <2 x i64> %src2, <2 x i64> *%dest) { 71; CHECK-LABEL: vmovn64_t2: 72; CHECK: @ %bb.0: @ %entry 73; CHECK-NEXT: vmov.f32 s6, s0 74; CHECK-NEXT: vmov.f32 s7, s1 75; CHECK-NEXT: vstrw.32 q1, [r0] 76; CHECK-NEXT: bx lr 77entry: 78 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 2, i32 0> 79 store <2 x i64> %out, <2 x i64> *%dest, align 8 80 ret void 81} 82 83define arm_aapcs_vfpcc void @vmovn64_b1(<2 x i64> %src1, <2 x i64> %src2, <2 x i64> *%dest) { 84; CHECK-LABEL: vmovn64_b1: 85; CHECK: @ %bb.0: @ %entry 86; CHECK-NEXT: vmov.f32 s2, s6 87; CHECK-NEXT: vmov.f32 s3, s7 88; CHECK-NEXT: vstrw.32 q0, [r0] 89; CHECK-NEXT: bx lr 90entry: 91 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 0, i32 3> 92 store <2 x i64> %out, <2 x i64> *%dest, align 8 93 ret void 94} 95 96define arm_aapcs_vfpcc void @vmovn64_b2(<2 x i64> %src1, <2 x i64> %src2, <2 x i64> *%dest) { 97; CHECK-LABEL: vmovn64_b2: 98; CHECK: @ %bb.0: @ %entry 99; CHECK-NEXT: vmov.f32 s8, s6 100; CHECK-NEXT: vmov.f32 s9, s7 101; CHECK-NEXT: vmov.f32 s10, s0 102; CHECK-NEXT: vmov.f32 s11, s1 103; CHECK-NEXT: vstrw.32 q2, [r0] 104; CHECK-NEXT: bx lr 105entry: 106 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 3, i32 0> 107 store <2 x i64> %out, <2 x i64> *%dest, align 8 108 ret void 109} 110 111define arm_aapcs_vfpcc void @vmovn64_b3(<2 x i64> %src1, <2 x i64> %src2, <2 x i64> *%dest) { 112; CHECK-LABEL: vmovn64_b3: 113; CHECK: @ %bb.0: @ %entry 114; CHECK-NEXT: vmov.f32 s8, s2 115; CHECK-NEXT: vmov.f32 s9, s3 116; CHECK-NEXT: vmov.f32 s10, s4 117; CHECK-NEXT: vmov.f32 s11, s5 118; CHECK-NEXT: vstrw.32 q2, [r0] 119; CHECK-NEXT: bx lr 120entry: 121 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 1, i32 2> 122 store <2 x i64> %out, <2 x i64> *%dest, align 8 123 ret void 124} 125 126define arm_aapcs_vfpcc void @vmovn64_b4(<2 x i64> %src1, <2 x i64> %src2, <2 x i64> *%dest) { 127; CHECK-LABEL: vmovn64_b4: 128; CHECK: @ %bb.0: @ %entry 129; CHECK-NEXT: vmov.f32 s6, s2 130; CHECK-NEXT: vmov.f32 s7, s3 131; CHECK-NEXT: vstrw.32 q1, [r0] 132; CHECK-NEXT: bx lr 133entry: 134 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 2, i32 1> 135 store <2 x i64> %out, <2 x i64> *%dest, align 8 136 ret void 137} 138 139 140 141define arm_aapcs_vfpcc void @vmovn32_t1(<4 x i32> %src1, <4 x i32> %src2, <4 x i32> *%dest) { 142; CHECK-LABEL: vmovn32_t1: 143; CHECK: @ %bb.0: @ %entry 144; CHECK-NEXT: vmov.f32 s1, s4 145; CHECK-NEXT: vmov.f32 s3, s6 146; CHECK-NEXT: vstrw.32 q0, [r0] 147; CHECK-NEXT: bx lr 148entry: 149 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 4, i32 2, i32 6> 150 store <4 x i32> %out, <4 x i32> *%dest, align 8 151 ret void 152} 153 154define arm_aapcs_vfpcc void @vmovn32_t2(<4 x i32> %src1, <4 x i32> %src2, <4 x i32> *%dest) { 155; CHECK-LABEL: vmovn32_t2: 156; CHECK: @ %bb.0: @ %entry 157; CHECK-NEXT: vmov.f32 s5, s0 158; CHECK-NEXT: vmov.f32 s7, s2 159; CHECK-NEXT: vstrw.32 q1, [r0] 160; CHECK-NEXT: bx lr 161entry: 162 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 0, i32 6, i32 2> 163 store <4 x i32> %out, <4 x i32> *%dest, align 8 164 ret void 165} 166 167define arm_aapcs_vfpcc void @vmovn32_b1(<4 x i32> %src1, <4 x i32> %src2, <4 x i32> *%dest) { 168; CHECK-LABEL: vmovn32_b1: 169; CHECK: @ %bb.0: @ %entry 170; CHECK-NEXT: vmov.f32 s1, s5 171; CHECK-NEXT: vmov.f32 s3, s7 172; CHECK-NEXT: vstrw.32 q0, [r0] 173; CHECK-NEXT: bx lr 174entry: 175 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 5, i32 2, i32 7> 176 store <4 x i32> %out, <4 x i32> *%dest, align 8 177 ret void 178} 179 180define arm_aapcs_vfpcc void @vmovn32_b2(<4 x i32> %src1, <4 x i32> %src2, <4 x i32> *%dest) { 181; CHECK-LABEL: vmovn32_b2: 182; CHECK: @ %bb.0: @ %entry 183; CHECK-NEXT: vmov.f32 s8, s5 184; CHECK-NEXT: vmov.f32 s9, s0 185; CHECK-NEXT: vmov.f32 s10, s7 186; CHECK-NEXT: vmov.f32 s11, s2 187; CHECK-NEXT: vstrw.32 q2, [r0] 188; CHECK-NEXT: bx lr 189entry: 190 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 5, i32 0, i32 7, i32 2> 191 store <4 x i32> %out, <4 x i32> *%dest, align 8 192 ret void 193} 194 195define arm_aapcs_vfpcc void @vmovn32_b3(<4 x i32> %src1, <4 x i32> %src2, <4 x i32> *%dest) { 196; CHECK-LABEL: vmovn32_b3: 197; CHECK: @ %bb.0: @ %entry 198; CHECK-NEXT: vmov.f32 s8, s1 199; CHECK-NEXT: vmov.f32 s9, s4 200; CHECK-NEXT: vmov.f32 s10, s3 201; CHECK-NEXT: vmov.f32 s11, s6 202; CHECK-NEXT: vstrw.32 q2, [r0] 203; CHECK-NEXT: bx lr 204entry: 205 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 1, i32 4, i32 3, i32 6> 206 store <4 x i32> %out, <4 x i32> *%dest, align 8 207 ret void 208} 209 210define arm_aapcs_vfpcc void @vmovn32_b4(<4 x i32> %src1, <4 x i32> %src2, <4 x i32> *%dest) { 211; CHECK-LABEL: vmovn32_b4: 212; CHECK: @ %bb.0: @ %entry 213; CHECK-NEXT: vmov.f32 s5, s1 214; CHECK-NEXT: vmov.f32 s7, s3 215; CHECK-NEXT: vstrw.32 q1, [r0] 216; CHECK-NEXT: bx lr 217entry: 218 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 1, i32 6, i32 3> 219 store <4 x i32> %out, <4 x i32> *%dest, align 8 220 ret void 221} 222 223 224 225 226define arm_aapcs_vfpcc void @vmovn16_t1(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) { 227; CHECK-LABEL: vmovn16_t1: 228; CHECK: @ %bb.0: @ %entry 229; CHECK-NEXT: vmovnt.i32 q0, q1 230; CHECK-NEXT: vstrw.32 q0, [r0] 231; CHECK-NEXT: bx lr 232entry: 233 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> 234 store <8 x i16> %out, <8 x i16> *%dest, align 8 235 ret void 236} 237 238define arm_aapcs_vfpcc void @vmovn16_t2(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) { 239; CHECK-LABEL: vmovn16_t2: 240; CHECK: @ %bb.0: @ %entry 241; CHECK-NEXT: vmovnt.i32 q1, q0 242; CHECK-NEXT: vstrw.32 q1, [r0] 243; CHECK-NEXT: bx lr 244entry: 245 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 0, i32 10, i32 2, i32 12, i32 4, i32 14, i32 6> 246 store <8 x i16> %out, <8 x i16> *%dest, align 8 247 ret void 248} 249 250define arm_aapcs_vfpcc void @vmovn16_b1(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) { 251; CHECK-LABEL: vmovn16_b1: 252; CHECK: @ %bb.0: @ %entry 253; CHECK-NEXT: vmovnb.i32 q1, q0 254; CHECK-NEXT: vstrw.32 q1, [r0] 255; CHECK-NEXT: bx lr 256entry: 257 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15> 258 store <8 x i16> %out, <8 x i16> *%dest, align 8 259 ret void 260} 261 262define arm_aapcs_vfpcc void @vmovn16_b2(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) { 263; CHECK-LABEL: vmovn16_b2: 264; CHECK: @ %bb.0: @ %entry 265; CHECK-NEXT: vmov.u16 r1, q1[1] 266; CHECK-NEXT: vmov.16 q2[0], r1 267; CHECK-NEXT: vmov.u16 r1, q0[0] 268; CHECK-NEXT: vmov.16 q2[1], r1 269; CHECK-NEXT: vmov.u16 r1, q1[3] 270; CHECK-NEXT: vmov.16 q2[2], r1 271; CHECK-NEXT: vmov.u16 r1, q0[2] 272; CHECK-NEXT: vmov.16 q2[3], r1 273; CHECK-NEXT: vmov.u16 r1, q1[5] 274; CHECK-NEXT: vmov.16 q2[4], r1 275; CHECK-NEXT: vmov.u16 r1, q0[4] 276; CHECK-NEXT: vmov.16 q2[5], r1 277; CHECK-NEXT: vmov.u16 r1, q1[7] 278; CHECK-NEXT: vmov.16 q2[6], r1 279; CHECK-NEXT: vmov.u16 r1, q0[6] 280; CHECK-NEXT: vmov.16 q2[7], r1 281; CHECK-NEXT: vstrw.32 q2, [r0] 282; CHECK-NEXT: bx lr 283entry: 284 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 9, i32 0, i32 11, i32 2, i32 13, i32 4, i32 15, i32 6> 285 store <8 x i16> %out, <8 x i16> *%dest, align 8 286 ret void 287} 288 289define arm_aapcs_vfpcc void @vmovn16_b3(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) { 290; CHECK-LABEL: vmovn16_b3: 291; CHECK: @ %bb.0: @ %entry 292; CHECK-NEXT: vmov.u16 r1, q0[1] 293; CHECK-NEXT: vmov.16 q2[0], r1 294; CHECK-NEXT: vmov.u16 r1, q1[0] 295; CHECK-NEXT: vmov.16 q2[1], r1 296; CHECK-NEXT: vmov.u16 r1, q0[3] 297; CHECK-NEXT: vmov.16 q2[2], r1 298; CHECK-NEXT: vmov.u16 r1, q1[2] 299; CHECK-NEXT: vmov.16 q2[3], r1 300; CHECK-NEXT: vmov.u16 r1, q0[5] 301; CHECK-NEXT: vmov.16 q2[4], r1 302; CHECK-NEXT: vmov.u16 r1, q1[4] 303; CHECK-NEXT: vmov.16 q2[5], r1 304; CHECK-NEXT: vmov.u16 r1, q0[7] 305; CHECK-NEXT: vmov.16 q2[6], r1 306; CHECK-NEXT: vmov.u16 r1, q1[6] 307; CHECK-NEXT: vmov.16 q2[7], r1 308; CHECK-NEXT: vstrw.32 q2, [r0] 309; CHECK-NEXT: bx lr 310entry: 311 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14> 312 store <8 x i16> %out, <8 x i16> *%dest, align 8 313 ret void 314} 315 316define arm_aapcs_vfpcc void @vmovn16_b4(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) { 317; CHECK-LABEL: vmovn16_b4: 318; CHECK: @ %bb.0: @ %entry 319; CHECK-NEXT: vmovnb.i32 q0, q1 320; CHECK-NEXT: vstrw.32 q0, [r0] 321; CHECK-NEXT: bx lr 322entry: 323 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7> 324 store <8 x i16> %out, <8 x i16> *%dest, align 8 325 ret void 326} 327 328 329define arm_aapcs_vfpcc void @vmovn8_b1(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> *%dest) { 330; CHECK-LABEL: vmovn8_b1: 331; CHECK: @ %bb.0: @ %entry 332; CHECK-NEXT: vmovnt.i16 q0, q1 333; CHECK-NEXT: vstrw.32 q0, [r0] 334; CHECK-NEXT: bx lr 335entry: 336 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> 337 store <16 x i8> %out, <16 x i8> *%dest, align 8 338 ret void 339} 340 341define arm_aapcs_vfpcc void @vmovn8_b2(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> *%dest) { 342; CHECK-LABEL: vmovn8_b2: 343; CHECK: @ %bb.0: @ %entry 344; CHECK-NEXT: vmovnt.i16 q1, q0 345; CHECK-NEXT: vstrw.32 q1, [r0] 346; CHECK-NEXT: bx lr 347entry: 348 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 0, i32 18, i32 2, i32 20, i32 4, i32 22, i32 6, i32 24, i32 8, i32 26, i32 10, i32 28, i32 12, i32 30, i32 14> 349 store <16 x i8> %out, <16 x i8> *%dest, align 8 350 ret void 351} 352 353define arm_aapcs_vfpcc void @vmovn8_t1(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> *%dest) { 354; CHECK-LABEL: vmovn8_t1: 355; CHECK: @ %bb.0: @ %entry 356; CHECK-NEXT: vmovnb.i16 q1, q0 357; CHECK-NEXT: vstrw.32 q1, [r0] 358; CHECK-NEXT: bx lr 359entry: 360 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31> 361 store <16 x i8> %out, <16 x i8> *%dest, align 8 362 ret void 363} 364 365define arm_aapcs_vfpcc void @vmovn8_t2(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> *%dest) { 366; CHECK-LABEL: vmovn8_t2: 367; CHECK: @ %bb.0: @ %entry 368; CHECK-NEXT: vmov.u8 r1, q1[1] 369; CHECK-NEXT: vmov.8 q2[0], r1 370; CHECK-NEXT: vmov.u8 r1, q0[0] 371; CHECK-NEXT: vmov.8 q2[1], r1 372; CHECK-NEXT: vmov.u8 r1, q1[3] 373; CHECK-NEXT: vmov.8 q2[2], r1 374; CHECK-NEXT: vmov.u8 r1, q0[2] 375; CHECK-NEXT: vmov.8 q2[3], r1 376; CHECK-NEXT: vmov.u8 r1, q1[5] 377; CHECK-NEXT: vmov.8 q2[4], r1 378; CHECK-NEXT: vmov.u8 r1, q0[4] 379; CHECK-NEXT: vmov.8 q2[5], r1 380; CHECK-NEXT: vmov.u8 r1, q1[7] 381; CHECK-NEXT: vmov.8 q2[6], r1 382; CHECK-NEXT: vmov.u8 r1, q0[6] 383; CHECK-NEXT: vmov.8 q2[7], r1 384; CHECK-NEXT: vmov.u8 r1, q1[9] 385; CHECK-NEXT: vmov.8 q2[8], r1 386; CHECK-NEXT: vmov.u8 r1, q0[8] 387; CHECK-NEXT: vmov.8 q2[9], r1 388; CHECK-NEXT: vmov.u8 r1, q1[11] 389; CHECK-NEXT: vmov.8 q2[10], r1 390; CHECK-NEXT: vmov.u8 r1, q0[10] 391; CHECK-NEXT: vmov.8 q2[11], r1 392; CHECK-NEXT: vmov.u8 r1, q1[13] 393; CHECK-NEXT: vmov.8 q2[12], r1 394; CHECK-NEXT: vmov.u8 r1, q0[12] 395; CHECK-NEXT: vmov.8 q2[13], r1 396; CHECK-NEXT: vmov.u8 r1, q1[15] 397; CHECK-NEXT: vmov.8 q2[14], r1 398; CHECK-NEXT: vmov.u8 r1, q0[14] 399; CHECK-NEXT: vmov.8 q2[15], r1 400; CHECK-NEXT: vstrw.32 q2, [r0] 401; CHECK-NEXT: bx lr 402entry: 403 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 17, i32 0, i32 19, i32 2, i32 21, i32 4, i32 23, i32 6, i32 25, i32 8, i32 27, i32 10, i32 29, i32 12, i32 31, i32 14> 404 store <16 x i8> %out, <16 x i8> *%dest, align 8 405 ret void 406} 407 408define arm_aapcs_vfpcc void @vmovn8_t3(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> *%dest) { 409; CHECK-LABEL: vmovn8_t3: 410; CHECK: @ %bb.0: @ %entry 411; CHECK-NEXT: vmov.u8 r1, q0[1] 412; CHECK-NEXT: vmov.8 q2[0], r1 413; CHECK-NEXT: vmov.u8 r1, q1[0] 414; CHECK-NEXT: vmov.8 q2[1], r1 415; CHECK-NEXT: vmov.u8 r1, q0[3] 416; CHECK-NEXT: vmov.8 q2[2], r1 417; CHECK-NEXT: vmov.u8 r1, q1[2] 418; CHECK-NEXT: vmov.8 q2[3], r1 419; CHECK-NEXT: vmov.u8 r1, q0[5] 420; CHECK-NEXT: vmov.8 q2[4], r1 421; CHECK-NEXT: vmov.u8 r1, q1[4] 422; CHECK-NEXT: vmov.8 q2[5], r1 423; CHECK-NEXT: vmov.u8 r1, q0[7] 424; CHECK-NEXT: vmov.8 q2[6], r1 425; CHECK-NEXT: vmov.u8 r1, q1[6] 426; CHECK-NEXT: vmov.8 q2[7], r1 427; CHECK-NEXT: vmov.u8 r1, q0[9] 428; CHECK-NEXT: vmov.8 q2[8], r1 429; CHECK-NEXT: vmov.u8 r1, q1[8] 430; CHECK-NEXT: vmov.8 q2[9], r1 431; CHECK-NEXT: vmov.u8 r1, q0[11] 432; CHECK-NEXT: vmov.8 q2[10], r1 433; CHECK-NEXT: vmov.u8 r1, q1[10] 434; CHECK-NEXT: vmov.8 q2[11], r1 435; CHECK-NEXT: vmov.u8 r1, q0[13] 436; CHECK-NEXT: vmov.8 q2[12], r1 437; CHECK-NEXT: vmov.u8 r1, q1[12] 438; CHECK-NEXT: vmov.8 q2[13], r1 439; CHECK-NEXT: vmov.u8 r1, q0[15] 440; CHECK-NEXT: vmov.8 q2[14], r1 441; CHECK-NEXT: vmov.u8 r1, q1[14] 442; CHECK-NEXT: vmov.8 q2[15], r1 443; CHECK-NEXT: vstrw.32 q2, [r0] 444; CHECK-NEXT: bx lr 445entry: 446 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 1, i32 16, i32 3, i32 18, i32 5, i32 20, i32 7, i32 22, i32 9, i32 24, i32 11, i32 26, i32 13, i32 28, i32 15, i32 30> 447 store <16 x i8> %out, <16 x i8> *%dest, align 8 448 ret void 449} 450 451define arm_aapcs_vfpcc void @vmovn8_t4(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> *%dest) { 452; CHECK-LABEL: vmovn8_t4: 453; CHECK: @ %bb.0: @ %entry 454; CHECK-NEXT: vmovnb.i16 q0, q1 455; CHECK-NEXT: vstrw.32 q0, [r0] 456; CHECK-NEXT: bx lr 457entry: 458 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 1, i32 18, i32 3, i32 20, i32 5, i32 22, i32 7, i32 24, i32 9, i32 26, i32 11, i32 28, i32 13, i32 30, i32 15> 459 store <16 x i8> %out, <16 x i8> *%dest, align 8 460 ret void 461} 462