1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s 3 4define arm_aapcs_vfpcc <4 x i32> @vsubqr_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 5; CHECK-LABEL: vsubqr_v4i32: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vsub.i32 q0, q0, r0 8; CHECK-NEXT: bx lr 9entry: 10 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 11 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 12 %c = sub <4 x i32> %src, %sp 13 ret <4 x i32> %c 14} 15 16define arm_aapcs_vfpcc <8 x i16> @vsubqr_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 17; CHECK-LABEL: vsubqr_v8i16: 18; CHECK: @ %bb.0: @ %entry 19; CHECK-NEXT: vsub.i16 q0, q0, r0 20; CHECK-NEXT: bx lr 21entry: 22 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 23 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 24 %c = sub <8 x i16> %src, %sp 25 ret <8 x i16> %c 26} 27 28define arm_aapcs_vfpcc <16 x i8> @vsubqr_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 29; CHECK-LABEL: vsubqr_v16i8: 30; CHECK: @ %bb.0: @ %entry 31; CHECK-NEXT: vsub.i8 q0, q0, r0 32; CHECK-NEXT: bx lr 33entry: 34 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 35 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 36 %c = sub <16 x i8> %src, %sp 37 ret <16 x i8> %c 38} 39 40define arm_aapcs_vfpcc <4 x i32> @vsubqr_v4i32_2(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { 41; CHECK-LABEL: vsubqr_v4i32_2: 42; CHECK: @ %bb.0: @ %entry 43; CHECK-NEXT: vdup.32 q1, r0 44; CHECK-NEXT: vsub.i32 q0, q1, q0 45; CHECK-NEXT: bx lr 46entry: 47 %i = insertelement <4 x i32> undef, i32 %src2, i32 0 48 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 49 %c = sub <4 x i32> %sp, %src 50 ret <4 x i32> %c 51} 52 53define arm_aapcs_vfpcc <8 x i16> @vsubqr_v8i16_2(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) { 54; CHECK-LABEL: vsubqr_v8i16_2: 55; CHECK: @ %bb.0: @ %entry 56; CHECK-NEXT: vdup.16 q1, r0 57; CHECK-NEXT: vsub.i16 q0, q1, q0 58; CHECK-NEXT: bx lr 59entry: 60 %i = insertelement <8 x i16> undef, i16 %src2, i32 0 61 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 62 %c = sub <8 x i16> %sp, %src 63 ret <8 x i16> %c 64} 65 66define arm_aapcs_vfpcc <16 x i8> @vsubqr_v16i8_2(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) { 67; CHECK-LABEL: vsubqr_v16i8_2: 68; CHECK: @ %bb.0: @ %entry 69; CHECK-NEXT: vdup.8 q1, r0 70; CHECK-NEXT: vsub.i8 q0, q1, q0 71; CHECK-NEXT: bx lr 72entry: 73 %i = insertelement <16 x i8> undef, i8 %src2, i32 0 74 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 75 %c = sub <16 x i8> %sp, %src 76 ret <16 x i8> %c 77} 78