1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s 2 3;;; Test vector divide intrinsic instructions 4;;; 5;;; Note: 6;;; We test VDIV*vvl, VDIV*vvl_v, VDIV*rvl, VDIV*rvl_v, VDIV*ivl, 7;;; VDIV*ivl_v, VDIV*vvml_v, VDIV*rvml_v, VDIV*ivml_v, VDIV*vrl, 8;;; VDIV*vrl_v, VDIV*vil, VDIV*vil_v, VDIV*vrml_v, and VDIV*viml_v 9;;; instructions. 10 11; Function Attrs: nounwind readnone 12define fastcc <256 x double> @vdivul_vvvl(<256 x double> %0, <256 x double> %1) { 13; CHECK-LABEL: vdivul_vvvl: 14; CHECK: # %bb.0: 15; CHECK-NEXT: lea %s0, 256 16; CHECK-NEXT: lvl %s0 17; CHECK-NEXT: vdivu.l %v0, %v0, %v1 18; CHECK-NEXT: b.l.t (, %s10) 19 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivul.vvvl(<256 x double> %0, <256 x double> %1, i32 256) 20 ret <256 x double> %3 21} 22 23; Function Attrs: nounwind readnone 24declare <256 x double> @llvm.ve.vl.vdivul.vvvl(<256 x double>, <256 x double>, i32) 25 26; Function Attrs: nounwind readnone 27define fastcc <256 x double> @vdivul_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { 28; CHECK-LABEL: vdivul_vvvvl: 29; CHECK: # %bb.0: 30; CHECK-NEXT: lea %s0, 128 31; CHECK-NEXT: lvl %s0 32; CHECK-NEXT: vdivu.l %v2, %v0, %v1 33; CHECK-NEXT: lea %s16, 256 34; CHECK-NEXT: lvl %s16 35; CHECK-NEXT: vor %v0, (0)1, %v2 36; CHECK-NEXT: b.l.t (, %s10) 37 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivul.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) 38 ret <256 x double> %4 39} 40 41; Function Attrs: nounwind readnone 42declare <256 x double> @llvm.ve.vl.vdivul.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) 43 44; Function Attrs: nounwind readnone 45define fastcc <256 x double> @vdivul_vsvl(i64 %0, <256 x double> %1) { 46; CHECK-LABEL: vdivul_vsvl: 47; CHECK: # %bb.0: 48; CHECK-NEXT: lea %s1, 256 49; CHECK-NEXT: lvl %s1 50; CHECK-NEXT: vdivu.l %v0, %s0, %v0 51; CHECK-NEXT: b.l.t (, %s10) 52 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivul.vsvl(i64 %0, <256 x double> %1, i32 256) 53 ret <256 x double> %3 54} 55 56; Function Attrs: nounwind readnone 57declare <256 x double> @llvm.ve.vl.vdivul.vsvl(i64, <256 x double>, i32) 58 59; Function Attrs: nounwind readnone 60define fastcc <256 x double> @vdivul_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) { 61; CHECK-LABEL: vdivul_vsvvl: 62; CHECK: # %bb.0: 63; CHECK-NEXT: lea %s1, 128 64; CHECK-NEXT: lvl %s1 65; CHECK-NEXT: vdivu.l %v1, %s0, %v0 66; CHECK-NEXT: lea %s16, 256 67; CHECK-NEXT: lvl %s16 68; CHECK-NEXT: vor %v0, (0)1, %v1 69; CHECK-NEXT: b.l.t (, %s10) 70 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivul.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128) 71 ret <256 x double> %4 72} 73 74; Function Attrs: nounwind readnone 75declare <256 x double> @llvm.ve.vl.vdivul.vsvvl(i64, <256 x double>, <256 x double>, i32) 76 77; Function Attrs: nounwind readnone 78define fastcc <256 x double> @vdivul_vsvl_imm(<256 x double> %0) { 79; CHECK-LABEL: vdivul_vsvl_imm: 80; CHECK: # %bb.0: 81; CHECK-NEXT: lea %s0, 256 82; CHECK-NEXT: lvl %s0 83; CHECK-NEXT: vdivu.l %v0, 8, %v0 84; CHECK-NEXT: b.l.t (, %s10) 85 %2 = tail call fast <256 x double> @llvm.ve.vl.vdivul.vsvl(i64 8, <256 x double> %0, i32 256) 86 ret <256 x double> %2 87} 88 89; Function Attrs: nounwind readnone 90define fastcc <256 x double> @vdivul_vsvvl_imm(<256 x double> %0, <256 x double> %1) { 91; CHECK-LABEL: vdivul_vsvvl_imm: 92; CHECK: # %bb.0: 93; CHECK-NEXT: lea %s0, 128 94; CHECK-NEXT: lvl %s0 95; CHECK-NEXT: vdivu.l %v1, 8, %v0 96; CHECK-NEXT: lea %s16, 256 97; CHECK-NEXT: lvl %s16 98; CHECK-NEXT: vor %v0, (0)1, %v1 99; CHECK-NEXT: b.l.t (, %s10) 100 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivul.vsvvl(i64 8, <256 x double> %0, <256 x double> %1, i32 128) 101 ret <256 x double> %3 102} 103 104; Function Attrs: nounwind readnone 105define fastcc <256 x double> @vdivul_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 106; CHECK-LABEL: vdivul_vvvmvl: 107; CHECK: # %bb.0: 108; CHECK-NEXT: lea %s0, 128 109; CHECK-NEXT: lvl %s0 110; CHECK-NEXT: vdivu.l %v2, %v0, %v1, %vm1 111; CHECK-NEXT: lea %s16, 256 112; CHECK-NEXT: lvl %s16 113; CHECK-NEXT: vor %v0, (0)1, %v2 114; CHECK-NEXT: b.l.t (, %s10) 115 %5 = tail call fast <256 x double> @llvm.ve.vl.vdivul.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 116 ret <256 x double> %5 117} 118 119; Function Attrs: nounwind readnone 120declare <256 x double> @llvm.ve.vl.vdivul.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) 121 122; Function Attrs: nounwind readnone 123define fastcc <256 x double> @vdivul_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 124; CHECK-LABEL: vdivul_vsvmvl: 125; CHECK: # %bb.0: 126; CHECK-NEXT: lea %s1, 128 127; CHECK-NEXT: lvl %s1 128; CHECK-NEXT: vdivu.l %v1, %s0, %v0, %vm1 129; CHECK-NEXT: lea %s16, 256 130; CHECK-NEXT: lvl %s16 131; CHECK-NEXT: vor %v0, (0)1, %v1 132; CHECK-NEXT: b.l.t (, %s10) 133 %5 = tail call fast <256 x double> @llvm.ve.vl.vdivul.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 134 ret <256 x double> %5 135} 136 137; Function Attrs: nounwind readnone 138declare <256 x double> @llvm.ve.vl.vdivul.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32) 139 140; Function Attrs: nounwind readnone 141define fastcc <256 x double> @vdivul_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 142; CHECK-LABEL: vdivul_vsvmvl_imm: 143; CHECK: # %bb.0: 144; CHECK-NEXT: lea %s0, 128 145; CHECK-NEXT: lvl %s0 146; CHECK-NEXT: vdivu.l %v1, 8, %v0, %vm1 147; CHECK-NEXT: lea %s16, 256 148; CHECK-NEXT: lvl %s16 149; CHECK-NEXT: vor %v0, (0)1, %v1 150; CHECK-NEXT: b.l.t (, %s10) 151 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivul.vsvmvl(i64 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 152 ret <256 x double> %4 153} 154 155; Function Attrs: nounwind readnone 156define fastcc <256 x double> @vdivul_vvsl(<256 x double> %0, i64 %1) { 157; CHECK-LABEL: vdivul_vvsl: 158; CHECK: # %bb.0: 159; CHECK-NEXT: lea %s1, 256 160; CHECK-NEXT: lvl %s1 161; CHECK-NEXT: vdivu.l %v0, %v0, %s0 162; CHECK-NEXT: b.l.t (, %s10) 163 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivul.vvsl(<256 x double> %0, i64 %1, i32 256) 164 ret <256 x double> %3 165} 166 167; Function Attrs: nounwind readnone 168declare <256 x double> @llvm.ve.vl.vdivul.vvsl(<256 x double>, i64, i32) 169 170; Function Attrs: nounwind readnone 171define fastcc <256 x double> @vdivul_vvsvl(<256 x double> %0, i64 %1, <256 x double> %2) { 172; CHECK-LABEL: vdivul_vvsvl: 173; CHECK: # %bb.0: 174; CHECK-NEXT: lea %s1, 128 175; CHECK-NEXT: lvl %s1 176; CHECK-NEXT: vdivu.l %v1, %v0, %s0 177; CHECK-NEXT: lea %s16, 256 178; CHECK-NEXT: lvl %s16 179; CHECK-NEXT: vor %v0, (0)1, %v1 180; CHECK-NEXT: b.l.t (, %s10) 181 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivul.vvsvl(<256 x double> %0, i64 %1, <256 x double> %2, i32 128) 182 ret <256 x double> %4 183} 184 185; Function Attrs: nounwind readnone 186declare <256 x double> @llvm.ve.vl.vdivul.vvsvl(<256 x double>, i64, <256 x double>, i32) 187 188; Function Attrs: nounwind readnone 189define fastcc <256 x double> @vdivul_vvsl_imm(<256 x double> %0) { 190; CHECK-LABEL: vdivul_vvsl_imm: 191; CHECK: # %bb.0: 192; CHECK-NEXT: lea %s0, 256 193; CHECK-NEXT: lvl %s0 194; CHECK-NEXT: vdivu.l %v0, %v0, 8 195; CHECK-NEXT: b.l.t (, %s10) 196 %2 = tail call fast <256 x double> @llvm.ve.vl.vdivul.vvsl(<256 x double> %0, i64 8, i32 256) 197 ret <256 x double> %2 198} 199 200; Function Attrs: nounwind readnone 201define fastcc <256 x double> @vdivul_vvsvl_imm(<256 x double> %0, <256 x double> %1) { 202; CHECK-LABEL: vdivul_vvsvl_imm: 203; CHECK: # %bb.0: 204; CHECK-NEXT: lea %s0, 128 205; CHECK-NEXT: lvl %s0 206; CHECK-NEXT: vdivu.l %v1, %v0, 8 207; CHECK-NEXT: lea %s16, 256 208; CHECK-NEXT: lvl %s16 209; CHECK-NEXT: vor %v0, (0)1, %v1 210; CHECK-NEXT: b.l.t (, %s10) 211 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivul.vvsvl(<256 x double> %0, i64 8, <256 x double> %1, i32 128) 212 ret <256 x double> %3 213} 214 215; Function Attrs: nounwind readnone 216define fastcc <256 x double> @vdivul_vvsmvl(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) { 217; CHECK-LABEL: vdivul_vvsmvl: 218; CHECK: # %bb.0: 219; CHECK-NEXT: lea %s1, 128 220; CHECK-NEXT: lvl %s1 221; CHECK-NEXT: vdivu.l %v1, %v0, %s0, %vm1 222; CHECK-NEXT: lea %s16, 256 223; CHECK-NEXT: lvl %s16 224; CHECK-NEXT: vor %v0, (0)1, %v1 225; CHECK-NEXT: b.l.t (, %s10) 226 %5 = tail call fast <256 x double> @llvm.ve.vl.vdivul.vvsmvl(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3, i32 128) 227 ret <256 x double> %5 228} 229 230; Function Attrs: nounwind readnone 231declare <256 x double> @llvm.ve.vl.vdivul.vvsmvl(<256 x double>, i64, <256 x i1>, <256 x double>, i32) 232 233; Function Attrs: nounwind readnone 234define fastcc <256 x double> @vdivul_vvsmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 235; CHECK-LABEL: vdivul_vvsmvl_imm: 236; CHECK: # %bb.0: 237; CHECK-NEXT: lea %s0, 128 238; CHECK-NEXT: lvl %s0 239; CHECK-NEXT: vdivu.l %v1, %v0, 8, %vm1 240; CHECK-NEXT: lea %s16, 256 241; CHECK-NEXT: lvl %s16 242; CHECK-NEXT: vor %v0, (0)1, %v1 243; CHECK-NEXT: b.l.t (, %s10) 244 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivul.vvsmvl(<256 x double> %0, i64 8, <256 x i1> %1, <256 x double> %2, i32 128) 245 ret <256 x double> %4 246} 247 248; Function Attrs: nounwind readnone 249define fastcc <256 x double> @vdivuw_vvvl(<256 x double> %0, <256 x double> %1) { 250; CHECK-LABEL: vdivuw_vvvl: 251; CHECK: # %bb.0: 252; CHECK-NEXT: lea %s0, 256 253; CHECK-NEXT: lvl %s0 254; CHECK-NEXT: vdivu.w %v0, %v0, %v1 255; CHECK-NEXT: b.l.t (, %s10) 256 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivuw.vvvl(<256 x double> %0, <256 x double> %1, i32 256) 257 ret <256 x double> %3 258} 259 260; Function Attrs: nounwind readnone 261declare <256 x double> @llvm.ve.vl.vdivuw.vvvl(<256 x double>, <256 x double>, i32) 262 263; Function Attrs: nounwind readnone 264define fastcc <256 x double> @vdivuw_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { 265; CHECK-LABEL: vdivuw_vvvvl: 266; CHECK: # %bb.0: 267; CHECK-NEXT: lea %s0, 128 268; CHECK-NEXT: lvl %s0 269; CHECK-NEXT: vdivu.w %v2, %v0, %v1 270; CHECK-NEXT: lea %s16, 256 271; CHECK-NEXT: lvl %s16 272; CHECK-NEXT: vor %v0, (0)1, %v2 273; CHECK-NEXT: b.l.t (, %s10) 274 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivuw.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) 275 ret <256 x double> %4 276} 277 278; Function Attrs: nounwind readnone 279declare <256 x double> @llvm.ve.vl.vdivuw.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) 280 281; Function Attrs: nounwind readnone 282define fastcc <256 x double> @vdivuw_vsvl(i32 signext %0, <256 x double> %1) { 283; CHECK-LABEL: vdivuw_vsvl: 284; CHECK: # %bb.0: 285; CHECK-NEXT: and %s0, %s0, (32)0 286; CHECK-NEXT: lea %s1, 256 287; CHECK-NEXT: lvl %s1 288; CHECK-NEXT: vdivu.w %v0, %s0, %v0 289; CHECK-NEXT: b.l.t (, %s10) 290 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivuw.vsvl(i32 %0, <256 x double> %1, i32 256) 291 ret <256 x double> %3 292} 293 294; Function Attrs: nounwind readnone 295declare <256 x double> @llvm.ve.vl.vdivuw.vsvl(i32, <256 x double>, i32) 296 297; Function Attrs: nounwind readnone 298define fastcc <256 x double> @vdivuw_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) { 299; CHECK-LABEL: vdivuw_vsvvl: 300; CHECK: # %bb.0: 301; CHECK-NEXT: and %s0, %s0, (32)0 302; CHECK-NEXT: lea %s1, 128 303; CHECK-NEXT: lvl %s1 304; CHECK-NEXT: vdivu.w %v1, %s0, %v0 305; CHECK-NEXT: lea %s16, 256 306; CHECK-NEXT: lvl %s16 307; CHECK-NEXT: vor %v0, (0)1, %v1 308; CHECK-NEXT: b.l.t (, %s10) 309 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivuw.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128) 310 ret <256 x double> %4 311} 312 313; Function Attrs: nounwind readnone 314declare <256 x double> @llvm.ve.vl.vdivuw.vsvvl(i32, <256 x double>, <256 x double>, i32) 315 316; Function Attrs: nounwind readnone 317define fastcc <256 x double> @vdivuw_vsvl_imm(<256 x double> %0) { 318; CHECK-LABEL: vdivuw_vsvl_imm: 319; CHECK: # %bb.0: 320; CHECK-NEXT: lea %s0, 256 321; CHECK-NEXT: lvl %s0 322; CHECK-NEXT: vdivu.w %v0, 8, %v0 323; CHECK-NEXT: b.l.t (, %s10) 324 %2 = tail call fast <256 x double> @llvm.ve.vl.vdivuw.vsvl(i32 8, <256 x double> %0, i32 256) 325 ret <256 x double> %2 326} 327 328; Function Attrs: nounwind readnone 329define fastcc <256 x double> @vdivuw_vsvvl_imm(<256 x double> %0, <256 x double> %1) { 330; CHECK-LABEL: vdivuw_vsvvl_imm: 331; CHECK: # %bb.0: 332; CHECK-NEXT: lea %s0, 128 333; CHECK-NEXT: lvl %s0 334; CHECK-NEXT: vdivu.w %v1, 8, %v0 335; CHECK-NEXT: lea %s16, 256 336; CHECK-NEXT: lvl %s16 337; CHECK-NEXT: vor %v0, (0)1, %v1 338; CHECK-NEXT: b.l.t (, %s10) 339 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivuw.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128) 340 ret <256 x double> %3 341} 342 343; Function Attrs: nounwind readnone 344define fastcc <256 x double> @vdivuw_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 345; CHECK-LABEL: vdivuw_vvvmvl: 346; CHECK: # %bb.0: 347; CHECK-NEXT: lea %s0, 128 348; CHECK-NEXT: lvl %s0 349; CHECK-NEXT: vdivu.w %v2, %v0, %v1, %vm1 350; CHECK-NEXT: lea %s16, 256 351; CHECK-NEXT: lvl %s16 352; CHECK-NEXT: vor %v0, (0)1, %v2 353; CHECK-NEXT: b.l.t (, %s10) 354 %5 = tail call fast <256 x double> @llvm.ve.vl.vdivuw.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 355 ret <256 x double> %5 356} 357 358; Function Attrs: nounwind readnone 359declare <256 x double> @llvm.ve.vl.vdivuw.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) 360 361; Function Attrs: nounwind readnone 362define fastcc <256 x double> @vdivuw_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 363; CHECK-LABEL: vdivuw_vsvmvl: 364; CHECK: # %bb.0: 365; CHECK-NEXT: and %s0, %s0, (32)0 366; CHECK-NEXT: lea %s1, 128 367; CHECK-NEXT: lvl %s1 368; CHECK-NEXT: vdivu.w %v1, %s0, %v0, %vm1 369; CHECK-NEXT: lea %s16, 256 370; CHECK-NEXT: lvl %s16 371; CHECK-NEXT: vor %v0, (0)1, %v1 372; CHECK-NEXT: b.l.t (, %s10) 373 %5 = tail call fast <256 x double> @llvm.ve.vl.vdivuw.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 374 ret <256 x double> %5 375} 376 377; Function Attrs: nounwind readnone 378declare <256 x double> @llvm.ve.vl.vdivuw.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32) 379 380; Function Attrs: nounwind readnone 381define fastcc <256 x double> @vdivuw_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 382; CHECK-LABEL: vdivuw_vsvmvl_imm: 383; CHECK: # %bb.0: 384; CHECK-NEXT: lea %s0, 128 385; CHECK-NEXT: lvl %s0 386; CHECK-NEXT: vdivu.w %v1, 8, %v0, %vm1 387; CHECK-NEXT: lea %s16, 256 388; CHECK-NEXT: lvl %s16 389; CHECK-NEXT: vor %v0, (0)1, %v1 390; CHECK-NEXT: b.l.t (, %s10) 391 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivuw.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 392 ret <256 x double> %4 393} 394 395; Function Attrs: nounwind readnone 396define fastcc <256 x double> @vdivuw_vvsl(<256 x double> %0, i32 signext %1) { 397; CHECK-LABEL: vdivuw_vvsl: 398; CHECK: # %bb.0: 399; CHECK-NEXT: and %s0, %s0, (32)0 400; CHECK-NEXT: lea %s1, 256 401; CHECK-NEXT: lvl %s1 402; CHECK-NEXT: vdivu.w %v0, %v0, %s0 403; CHECK-NEXT: b.l.t (, %s10) 404 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivuw.vvsl(<256 x double> %0, i32 %1, i32 256) 405 ret <256 x double> %3 406} 407 408; Function Attrs: nounwind readnone 409declare <256 x double> @llvm.ve.vl.vdivuw.vvsl(<256 x double>, i32, i32) 410 411; Function Attrs: nounwind readnone 412define fastcc <256 x double> @vdivuw_vvsvl(<256 x double> %0, i32 signext %1, <256 x double> %2) { 413; CHECK-LABEL: vdivuw_vvsvl: 414; CHECK: # %bb.0: 415; CHECK-NEXT: and %s0, %s0, (32)0 416; CHECK-NEXT: lea %s1, 128 417; CHECK-NEXT: lvl %s1 418; CHECK-NEXT: vdivu.w %v1, %v0, %s0 419; CHECK-NEXT: lea %s16, 256 420; CHECK-NEXT: lvl %s16 421; CHECK-NEXT: vor %v0, (0)1, %v1 422; CHECK-NEXT: b.l.t (, %s10) 423 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivuw.vvsvl(<256 x double> %0, i32 %1, <256 x double> %2, i32 128) 424 ret <256 x double> %4 425} 426 427; Function Attrs: nounwind readnone 428declare <256 x double> @llvm.ve.vl.vdivuw.vvsvl(<256 x double>, i32, <256 x double>, i32) 429 430; Function Attrs: nounwind readnone 431define fastcc <256 x double> @vdivuw_vvsl_imm(<256 x double> %0) { 432; CHECK-LABEL: vdivuw_vvsl_imm: 433; CHECK: # %bb.0: 434; CHECK-NEXT: lea %s0, 256 435; CHECK-NEXT: lvl %s0 436; CHECK-NEXT: vdivu.w %v0, %v0, 8 437; CHECK-NEXT: b.l.t (, %s10) 438 %2 = tail call fast <256 x double> @llvm.ve.vl.vdivuw.vvsl(<256 x double> %0, i32 8, i32 256) 439 ret <256 x double> %2 440} 441 442; Function Attrs: nounwind readnone 443define fastcc <256 x double> @vdivuw_vvsvl_imm(<256 x double> %0, <256 x double> %1) { 444; CHECK-LABEL: vdivuw_vvsvl_imm: 445; CHECK: # %bb.0: 446; CHECK-NEXT: lea %s0, 128 447; CHECK-NEXT: lvl %s0 448; CHECK-NEXT: vdivu.w %v1, %v0, 8 449; CHECK-NEXT: lea %s16, 256 450; CHECK-NEXT: lvl %s16 451; CHECK-NEXT: vor %v0, (0)1, %v1 452; CHECK-NEXT: b.l.t (, %s10) 453 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivuw.vvsvl(<256 x double> %0, i32 8, <256 x double> %1, i32 128) 454 ret <256 x double> %3 455} 456 457; Function Attrs: nounwind readnone 458define fastcc <256 x double> @vdivuw_vvsmvl(<256 x double> %0, i32 signext %1, <256 x i1> %2, <256 x double> %3) { 459; CHECK-LABEL: vdivuw_vvsmvl: 460; CHECK: # %bb.0: 461; CHECK-NEXT: and %s0, %s0, (32)0 462; CHECK-NEXT: lea %s1, 128 463; CHECK-NEXT: lvl %s1 464; CHECK-NEXT: vdivu.w %v1, %v0, %s0, %vm1 465; CHECK-NEXT: lea %s16, 256 466; CHECK-NEXT: lvl %s16 467; CHECK-NEXT: vor %v0, (0)1, %v1 468; CHECK-NEXT: b.l.t (, %s10) 469 %5 = tail call fast <256 x double> @llvm.ve.vl.vdivuw.vvsmvl(<256 x double> %0, i32 %1, <256 x i1> %2, <256 x double> %3, i32 128) 470 ret <256 x double> %5 471} 472 473; Function Attrs: nounwind readnone 474declare <256 x double> @llvm.ve.vl.vdivuw.vvsmvl(<256 x double>, i32, <256 x i1>, <256 x double>, i32) 475 476; Function Attrs: nounwind readnone 477define fastcc <256 x double> @vdivuw_vvsmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 478; CHECK-LABEL: vdivuw_vvsmvl_imm: 479; CHECK: # %bb.0: 480; CHECK-NEXT: lea %s0, 128 481; CHECK-NEXT: lvl %s0 482; CHECK-NEXT: vdivu.w %v1, %v0, 8, %vm1 483; CHECK-NEXT: lea %s16, 256 484; CHECK-NEXT: lvl %s16 485; CHECK-NEXT: vor %v0, (0)1, %v1 486; CHECK-NEXT: b.l.t (, %s10) 487 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivuw.vvsmvl(<256 x double> %0, i32 8, <256 x i1> %1, <256 x double> %2, i32 128) 488 ret <256 x double> %4 489} 490 491; Function Attrs: nounwind readnone 492define fastcc <256 x double> @vdivswsx_vvvl(<256 x double> %0, <256 x double> %1) { 493; CHECK-LABEL: vdivswsx_vvvl: 494; CHECK: # %bb.0: 495; CHECK-NEXT: lea %s0, 256 496; CHECK-NEXT: lvl %s0 497; CHECK-NEXT: vdivs.w.sx %v0, %v0, %v1 498; CHECK-NEXT: b.l.t (, %s10) 499 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivswsx.vvvl(<256 x double> %0, <256 x double> %1, i32 256) 500 ret <256 x double> %3 501} 502 503; Function Attrs: nounwind readnone 504declare <256 x double> @llvm.ve.vl.vdivswsx.vvvl(<256 x double>, <256 x double>, i32) 505 506; Function Attrs: nounwind readnone 507define fastcc <256 x double> @vdivswsx_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { 508; CHECK-LABEL: vdivswsx_vvvvl: 509; CHECK: # %bb.0: 510; CHECK-NEXT: lea %s0, 128 511; CHECK-NEXT: lvl %s0 512; CHECK-NEXT: vdivs.w.sx %v2, %v0, %v1 513; CHECK-NEXT: lea %s16, 256 514; CHECK-NEXT: lvl %s16 515; CHECK-NEXT: vor %v0, (0)1, %v2 516; CHECK-NEXT: b.l.t (, %s10) 517 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivswsx.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) 518 ret <256 x double> %4 519} 520 521; Function Attrs: nounwind readnone 522declare <256 x double> @llvm.ve.vl.vdivswsx.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) 523 524; Function Attrs: nounwind readnone 525define fastcc <256 x double> @vdivswsx_vsvl(i32 signext %0, <256 x double> %1) { 526; CHECK-LABEL: vdivswsx_vsvl: 527; CHECK: # %bb.0: 528; CHECK-NEXT: and %s0, %s0, (32)0 529; CHECK-NEXT: lea %s1, 256 530; CHECK-NEXT: lvl %s1 531; CHECK-NEXT: vdivs.w.sx %v0, %s0, %v0 532; CHECK-NEXT: b.l.t (, %s10) 533 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivswsx.vsvl(i32 %0, <256 x double> %1, i32 256) 534 ret <256 x double> %3 535} 536 537; Function Attrs: nounwind readnone 538declare <256 x double> @llvm.ve.vl.vdivswsx.vsvl(i32, <256 x double>, i32) 539 540; Function Attrs: nounwind readnone 541define fastcc <256 x double> @vdivswsx_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) { 542; CHECK-LABEL: vdivswsx_vsvvl: 543; CHECK: # %bb.0: 544; CHECK-NEXT: and %s0, %s0, (32)0 545; CHECK-NEXT: lea %s1, 128 546; CHECK-NEXT: lvl %s1 547; CHECK-NEXT: vdivs.w.sx %v1, %s0, %v0 548; CHECK-NEXT: lea %s16, 256 549; CHECK-NEXT: lvl %s16 550; CHECK-NEXT: vor %v0, (0)1, %v1 551; CHECK-NEXT: b.l.t (, %s10) 552 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivswsx.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128) 553 ret <256 x double> %4 554} 555 556; Function Attrs: nounwind readnone 557declare <256 x double> @llvm.ve.vl.vdivswsx.vsvvl(i32, <256 x double>, <256 x double>, i32) 558 559; Function Attrs: nounwind readnone 560define fastcc <256 x double> @vdivswsx_vsvl_imm(<256 x double> %0) { 561; CHECK-LABEL: vdivswsx_vsvl_imm: 562; CHECK: # %bb.0: 563; CHECK-NEXT: lea %s0, 256 564; CHECK-NEXT: lvl %s0 565; CHECK-NEXT: vdivs.w.sx %v0, 8, %v0 566; CHECK-NEXT: b.l.t (, %s10) 567 %2 = tail call fast <256 x double> @llvm.ve.vl.vdivswsx.vsvl(i32 8, <256 x double> %0, i32 256) 568 ret <256 x double> %2 569} 570 571; Function Attrs: nounwind readnone 572define fastcc <256 x double> @vdivswsx_vsvvl_imm(<256 x double> %0, <256 x double> %1) { 573; CHECK-LABEL: vdivswsx_vsvvl_imm: 574; CHECK: # %bb.0: 575; CHECK-NEXT: lea %s0, 128 576; CHECK-NEXT: lvl %s0 577; CHECK-NEXT: vdivs.w.sx %v1, 8, %v0 578; CHECK-NEXT: lea %s16, 256 579; CHECK-NEXT: lvl %s16 580; CHECK-NEXT: vor %v0, (0)1, %v1 581; CHECK-NEXT: b.l.t (, %s10) 582 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivswsx.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128) 583 ret <256 x double> %3 584} 585 586; Function Attrs: nounwind readnone 587define fastcc <256 x double> @vdivswsx_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 588; CHECK-LABEL: vdivswsx_vvvmvl: 589; CHECK: # %bb.0: 590; CHECK-NEXT: lea %s0, 128 591; CHECK-NEXT: lvl %s0 592; CHECK-NEXT: vdivs.w.sx %v2, %v0, %v1, %vm1 593; CHECK-NEXT: lea %s16, 256 594; CHECK-NEXT: lvl %s16 595; CHECK-NEXT: vor %v0, (0)1, %v2 596; CHECK-NEXT: b.l.t (, %s10) 597 %5 = tail call fast <256 x double> @llvm.ve.vl.vdivswsx.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 598 ret <256 x double> %5 599} 600 601; Function Attrs: nounwind readnone 602declare <256 x double> @llvm.ve.vl.vdivswsx.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) 603 604; Function Attrs: nounwind readnone 605define fastcc <256 x double> @vdivswsx_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 606; CHECK-LABEL: vdivswsx_vsvmvl: 607; CHECK: # %bb.0: 608; CHECK-NEXT: and %s0, %s0, (32)0 609; CHECK-NEXT: lea %s1, 128 610; CHECK-NEXT: lvl %s1 611; CHECK-NEXT: vdivs.w.sx %v1, %s0, %v0, %vm1 612; CHECK-NEXT: lea %s16, 256 613; CHECK-NEXT: lvl %s16 614; CHECK-NEXT: vor %v0, (0)1, %v1 615; CHECK-NEXT: b.l.t (, %s10) 616 %5 = tail call fast <256 x double> @llvm.ve.vl.vdivswsx.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 617 ret <256 x double> %5 618} 619 620; Function Attrs: nounwind readnone 621declare <256 x double> @llvm.ve.vl.vdivswsx.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32) 622 623; Function Attrs: nounwind readnone 624define fastcc <256 x double> @vdivswsx_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 625; CHECK-LABEL: vdivswsx_vsvmvl_imm: 626; CHECK: # %bb.0: 627; CHECK-NEXT: lea %s0, 128 628; CHECK-NEXT: lvl %s0 629; CHECK-NEXT: vdivs.w.sx %v1, 8, %v0, %vm1 630; CHECK-NEXT: lea %s16, 256 631; CHECK-NEXT: lvl %s16 632; CHECK-NEXT: vor %v0, (0)1, %v1 633; CHECK-NEXT: b.l.t (, %s10) 634 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivswsx.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 635 ret <256 x double> %4 636} 637 638; Function Attrs: nounwind readnone 639define fastcc <256 x double> @vdivswsx_vvsl(<256 x double> %0, i32 signext %1) { 640; CHECK-LABEL: vdivswsx_vvsl: 641; CHECK: # %bb.0: 642; CHECK-NEXT: and %s0, %s0, (32)0 643; CHECK-NEXT: lea %s1, 256 644; CHECK-NEXT: lvl %s1 645; CHECK-NEXT: vdivs.w.sx %v0, %v0, %s0 646; CHECK-NEXT: b.l.t (, %s10) 647 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivswsx.vvsl(<256 x double> %0, i32 %1, i32 256) 648 ret <256 x double> %3 649} 650 651; Function Attrs: nounwind readnone 652declare <256 x double> @llvm.ve.vl.vdivswsx.vvsl(<256 x double>, i32, i32) 653 654; Function Attrs: nounwind readnone 655define fastcc <256 x double> @vdivswsx_vvsvl(<256 x double> %0, i32 signext %1, <256 x double> %2) { 656; CHECK-LABEL: vdivswsx_vvsvl: 657; CHECK: # %bb.0: 658; CHECK-NEXT: and %s0, %s0, (32)0 659; CHECK-NEXT: lea %s1, 128 660; CHECK-NEXT: lvl %s1 661; CHECK-NEXT: vdivs.w.sx %v1, %v0, %s0 662; CHECK-NEXT: lea %s16, 256 663; CHECK-NEXT: lvl %s16 664; CHECK-NEXT: vor %v0, (0)1, %v1 665; CHECK-NEXT: b.l.t (, %s10) 666 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivswsx.vvsvl(<256 x double> %0, i32 %1, <256 x double> %2, i32 128) 667 ret <256 x double> %4 668} 669 670; Function Attrs: nounwind readnone 671declare <256 x double> @llvm.ve.vl.vdivswsx.vvsvl(<256 x double>, i32, <256 x double>, i32) 672 673; Function Attrs: nounwind readnone 674define fastcc <256 x double> @vdivswsx_vvsl_imm(<256 x double> %0) { 675; CHECK-LABEL: vdivswsx_vvsl_imm: 676; CHECK: # %bb.0: 677; CHECK-NEXT: lea %s0, 256 678; CHECK-NEXT: lvl %s0 679; CHECK-NEXT: vdivs.w.sx %v0, %v0, 8 680; CHECK-NEXT: b.l.t (, %s10) 681 %2 = tail call fast <256 x double> @llvm.ve.vl.vdivswsx.vvsl(<256 x double> %0, i32 8, i32 256) 682 ret <256 x double> %2 683} 684 685; Function Attrs: nounwind readnone 686define fastcc <256 x double> @vdivswsx_vvsvl_imm(<256 x double> %0, <256 x double> %1) { 687; CHECK-LABEL: vdivswsx_vvsvl_imm: 688; CHECK: # %bb.0: 689; CHECK-NEXT: lea %s0, 128 690; CHECK-NEXT: lvl %s0 691; CHECK-NEXT: vdivs.w.sx %v1, %v0, 8 692; CHECK-NEXT: lea %s16, 256 693; CHECK-NEXT: lvl %s16 694; CHECK-NEXT: vor %v0, (0)1, %v1 695; CHECK-NEXT: b.l.t (, %s10) 696 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivswsx.vvsvl(<256 x double> %0, i32 8, <256 x double> %1, i32 128) 697 ret <256 x double> %3 698} 699 700; Function Attrs: nounwind readnone 701define fastcc <256 x double> @vdivswsx_vvsmvl(<256 x double> %0, i32 signext %1, <256 x i1> %2, <256 x double> %3) { 702; CHECK-LABEL: vdivswsx_vvsmvl: 703; CHECK: # %bb.0: 704; CHECK-NEXT: and %s0, %s0, (32)0 705; CHECK-NEXT: lea %s1, 128 706; CHECK-NEXT: lvl %s1 707; CHECK-NEXT: vdivs.w.sx %v1, %v0, %s0, %vm1 708; CHECK-NEXT: lea %s16, 256 709; CHECK-NEXT: lvl %s16 710; CHECK-NEXT: vor %v0, (0)1, %v1 711; CHECK-NEXT: b.l.t (, %s10) 712 %5 = tail call fast <256 x double> @llvm.ve.vl.vdivswsx.vvsmvl(<256 x double> %0, i32 %1, <256 x i1> %2, <256 x double> %3, i32 128) 713 ret <256 x double> %5 714} 715 716; Function Attrs: nounwind readnone 717declare <256 x double> @llvm.ve.vl.vdivswsx.vvsmvl(<256 x double>, i32, <256 x i1>, <256 x double>, i32) 718 719; Function Attrs: nounwind readnone 720define fastcc <256 x double> @vdivswsx_vvsmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 721; CHECK-LABEL: vdivswsx_vvsmvl_imm: 722; CHECK: # %bb.0: 723; CHECK-NEXT: lea %s0, 128 724; CHECK-NEXT: lvl %s0 725; CHECK-NEXT: vdivs.w.sx %v1, %v0, 8, %vm1 726; CHECK-NEXT: lea %s16, 256 727; CHECK-NEXT: lvl %s16 728; CHECK-NEXT: vor %v0, (0)1, %v1 729; CHECK-NEXT: b.l.t (, %s10) 730 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivswsx.vvsmvl(<256 x double> %0, i32 8, <256 x i1> %1, <256 x double> %2, i32 128) 731 ret <256 x double> %4 732} 733 734; Function Attrs: nounwind readnone 735define fastcc <256 x double> @vdivswzx_vvvl(<256 x double> %0, <256 x double> %1) { 736; CHECK-LABEL: vdivswzx_vvvl: 737; CHECK: # %bb.0: 738; CHECK-NEXT: lea %s0, 256 739; CHECK-NEXT: lvl %s0 740; CHECK-NEXT: vdivs.w.zx %v0, %v0, %v1 741; CHECK-NEXT: b.l.t (, %s10) 742 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivswzx.vvvl(<256 x double> %0, <256 x double> %1, i32 256) 743 ret <256 x double> %3 744} 745 746; Function Attrs: nounwind readnone 747declare <256 x double> @llvm.ve.vl.vdivswzx.vvvl(<256 x double>, <256 x double>, i32) 748 749; Function Attrs: nounwind readnone 750define fastcc <256 x double> @vdivswzx_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { 751; CHECK-LABEL: vdivswzx_vvvvl: 752; CHECK: # %bb.0: 753; CHECK-NEXT: lea %s0, 128 754; CHECK-NEXT: lvl %s0 755; CHECK-NEXT: vdivs.w.zx %v2, %v0, %v1 756; CHECK-NEXT: lea %s16, 256 757; CHECK-NEXT: lvl %s16 758; CHECK-NEXT: vor %v0, (0)1, %v2 759; CHECK-NEXT: b.l.t (, %s10) 760 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivswzx.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) 761 ret <256 x double> %4 762} 763 764; Function Attrs: nounwind readnone 765declare <256 x double> @llvm.ve.vl.vdivswzx.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) 766 767; Function Attrs: nounwind readnone 768define fastcc <256 x double> @vdivswzx_vsvl(i32 signext %0, <256 x double> %1) { 769; CHECK-LABEL: vdivswzx_vsvl: 770; CHECK: # %bb.0: 771; CHECK-NEXT: and %s0, %s0, (32)0 772; CHECK-NEXT: lea %s1, 256 773; CHECK-NEXT: lvl %s1 774; CHECK-NEXT: vdivs.w.zx %v0, %s0, %v0 775; CHECK-NEXT: b.l.t (, %s10) 776 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivswzx.vsvl(i32 %0, <256 x double> %1, i32 256) 777 ret <256 x double> %3 778} 779 780; Function Attrs: nounwind readnone 781declare <256 x double> @llvm.ve.vl.vdivswzx.vsvl(i32, <256 x double>, i32) 782 783; Function Attrs: nounwind readnone 784define fastcc <256 x double> @vdivswzx_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) { 785; CHECK-LABEL: vdivswzx_vsvvl: 786; CHECK: # %bb.0: 787; CHECK-NEXT: and %s0, %s0, (32)0 788; CHECK-NEXT: lea %s1, 128 789; CHECK-NEXT: lvl %s1 790; CHECK-NEXT: vdivs.w.zx %v1, %s0, %v0 791; CHECK-NEXT: lea %s16, 256 792; CHECK-NEXT: lvl %s16 793; CHECK-NEXT: vor %v0, (0)1, %v1 794; CHECK-NEXT: b.l.t (, %s10) 795 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivswzx.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128) 796 ret <256 x double> %4 797} 798 799; Function Attrs: nounwind readnone 800declare <256 x double> @llvm.ve.vl.vdivswzx.vsvvl(i32, <256 x double>, <256 x double>, i32) 801 802; Function Attrs: nounwind readnone 803define fastcc <256 x double> @vdivswzx_vsvl_imm(<256 x double> %0) { 804; CHECK-LABEL: vdivswzx_vsvl_imm: 805; CHECK: # %bb.0: 806; CHECK-NEXT: lea %s0, 256 807; CHECK-NEXT: lvl %s0 808; CHECK-NEXT: vdivs.w.zx %v0, 8, %v0 809; CHECK-NEXT: b.l.t (, %s10) 810 %2 = tail call fast <256 x double> @llvm.ve.vl.vdivswzx.vsvl(i32 8, <256 x double> %0, i32 256) 811 ret <256 x double> %2 812} 813 814; Function Attrs: nounwind readnone 815define fastcc <256 x double> @vdivswzx_vsvvl_imm(<256 x double> %0, <256 x double> %1) { 816; CHECK-LABEL: vdivswzx_vsvvl_imm: 817; CHECK: # %bb.0: 818; CHECK-NEXT: lea %s0, 128 819; CHECK-NEXT: lvl %s0 820; CHECK-NEXT: vdivs.w.zx %v1, 8, %v0 821; CHECK-NEXT: lea %s16, 256 822; CHECK-NEXT: lvl %s16 823; CHECK-NEXT: vor %v0, (0)1, %v1 824; CHECK-NEXT: b.l.t (, %s10) 825 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivswzx.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128) 826 ret <256 x double> %3 827} 828 829; Function Attrs: nounwind readnone 830define fastcc <256 x double> @vdivswzx_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 831; CHECK-LABEL: vdivswzx_vvvmvl: 832; CHECK: # %bb.0: 833; CHECK-NEXT: lea %s0, 128 834; CHECK-NEXT: lvl %s0 835; CHECK-NEXT: vdivs.w.zx %v2, %v0, %v1, %vm1 836; CHECK-NEXT: lea %s16, 256 837; CHECK-NEXT: lvl %s16 838; CHECK-NEXT: vor %v0, (0)1, %v2 839; CHECK-NEXT: b.l.t (, %s10) 840 %5 = tail call fast <256 x double> @llvm.ve.vl.vdivswzx.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 841 ret <256 x double> %5 842} 843 844; Function Attrs: nounwind readnone 845declare <256 x double> @llvm.ve.vl.vdivswzx.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) 846 847; Function Attrs: nounwind readnone 848define fastcc <256 x double> @vdivswzx_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 849; CHECK-LABEL: vdivswzx_vsvmvl: 850; CHECK: # %bb.0: 851; CHECK-NEXT: and %s0, %s0, (32)0 852; CHECK-NEXT: lea %s1, 128 853; CHECK-NEXT: lvl %s1 854; CHECK-NEXT: vdivs.w.zx %v1, %s0, %v0, %vm1 855; CHECK-NEXT: lea %s16, 256 856; CHECK-NEXT: lvl %s16 857; CHECK-NEXT: vor %v0, (0)1, %v1 858; CHECK-NEXT: b.l.t (, %s10) 859 %5 = tail call fast <256 x double> @llvm.ve.vl.vdivswzx.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 860 ret <256 x double> %5 861} 862 863; Function Attrs: nounwind readnone 864declare <256 x double> @llvm.ve.vl.vdivswzx.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32) 865 866; Function Attrs: nounwind readnone 867define fastcc <256 x double> @vdivswzx_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 868; CHECK-LABEL: vdivswzx_vsvmvl_imm: 869; CHECK: # %bb.0: 870; CHECK-NEXT: lea %s0, 128 871; CHECK-NEXT: lvl %s0 872; CHECK-NEXT: vdivs.w.zx %v1, 8, %v0, %vm1 873; CHECK-NEXT: lea %s16, 256 874; CHECK-NEXT: lvl %s16 875; CHECK-NEXT: vor %v0, (0)1, %v1 876; CHECK-NEXT: b.l.t (, %s10) 877 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivswzx.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 878 ret <256 x double> %4 879} 880 881; Function Attrs: nounwind readnone 882define fastcc <256 x double> @vdivswzx_vvsl(<256 x double> %0, i32 signext %1) { 883; CHECK-LABEL: vdivswzx_vvsl: 884; CHECK: # %bb.0: 885; CHECK-NEXT: and %s0, %s0, (32)0 886; CHECK-NEXT: lea %s1, 256 887; CHECK-NEXT: lvl %s1 888; CHECK-NEXT: vdivs.w.zx %v0, %v0, %s0 889; CHECK-NEXT: b.l.t (, %s10) 890 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivswzx.vvsl(<256 x double> %0, i32 %1, i32 256) 891 ret <256 x double> %3 892} 893 894; Function Attrs: nounwind readnone 895declare <256 x double> @llvm.ve.vl.vdivswzx.vvsl(<256 x double>, i32, i32) 896 897; Function Attrs: nounwind readnone 898define fastcc <256 x double> @vdivswzx_vvsvl(<256 x double> %0, i32 signext %1, <256 x double> %2) { 899; CHECK-LABEL: vdivswzx_vvsvl: 900; CHECK: # %bb.0: 901; CHECK-NEXT: and %s0, %s0, (32)0 902; CHECK-NEXT: lea %s1, 128 903; CHECK-NEXT: lvl %s1 904; CHECK-NEXT: vdivs.w.zx %v1, %v0, %s0 905; CHECK-NEXT: lea %s16, 256 906; CHECK-NEXT: lvl %s16 907; CHECK-NEXT: vor %v0, (0)1, %v1 908; CHECK-NEXT: b.l.t (, %s10) 909 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivswzx.vvsvl(<256 x double> %0, i32 %1, <256 x double> %2, i32 128) 910 ret <256 x double> %4 911} 912 913; Function Attrs: nounwind readnone 914declare <256 x double> @llvm.ve.vl.vdivswzx.vvsvl(<256 x double>, i32, <256 x double>, i32) 915 916; Function Attrs: nounwind readnone 917define fastcc <256 x double> @vdivswzx_vvsl_imm(<256 x double> %0) { 918; CHECK-LABEL: vdivswzx_vvsl_imm: 919; CHECK: # %bb.0: 920; CHECK-NEXT: lea %s0, 256 921; CHECK-NEXT: lvl %s0 922; CHECK-NEXT: vdivs.w.zx %v0, %v0, 8 923; CHECK-NEXT: b.l.t (, %s10) 924 %2 = tail call fast <256 x double> @llvm.ve.vl.vdivswzx.vvsl(<256 x double> %0, i32 8, i32 256) 925 ret <256 x double> %2 926} 927 928; Function Attrs: nounwind readnone 929define fastcc <256 x double> @vdivswzx_vvsvl_imm(<256 x double> %0, <256 x double> %1) { 930; CHECK-LABEL: vdivswzx_vvsvl_imm: 931; CHECK: # %bb.0: 932; CHECK-NEXT: lea %s0, 128 933; CHECK-NEXT: lvl %s0 934; CHECK-NEXT: vdivs.w.zx %v1, %v0, 8 935; CHECK-NEXT: lea %s16, 256 936; CHECK-NEXT: lvl %s16 937; CHECK-NEXT: vor %v0, (0)1, %v1 938; CHECK-NEXT: b.l.t (, %s10) 939 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivswzx.vvsvl(<256 x double> %0, i32 8, <256 x double> %1, i32 128) 940 ret <256 x double> %3 941} 942 943; Function Attrs: nounwind readnone 944define fastcc <256 x double> @vdivswzx_vvsmvl(<256 x double> %0, i32 signext %1, <256 x i1> %2, <256 x double> %3) { 945; CHECK-LABEL: vdivswzx_vvsmvl: 946; CHECK: # %bb.0: 947; CHECK-NEXT: and %s0, %s0, (32)0 948; CHECK-NEXT: lea %s1, 128 949; CHECK-NEXT: lvl %s1 950; CHECK-NEXT: vdivs.w.zx %v1, %v0, %s0, %vm1 951; CHECK-NEXT: lea %s16, 256 952; CHECK-NEXT: lvl %s16 953; CHECK-NEXT: vor %v0, (0)1, %v1 954; CHECK-NEXT: b.l.t (, %s10) 955 %5 = tail call fast <256 x double> @llvm.ve.vl.vdivswzx.vvsmvl(<256 x double> %0, i32 %1, <256 x i1> %2, <256 x double> %3, i32 128) 956 ret <256 x double> %5 957} 958 959; Function Attrs: nounwind readnone 960declare <256 x double> @llvm.ve.vl.vdivswzx.vvsmvl(<256 x double>, i32, <256 x i1>, <256 x double>, i32) 961 962; Function Attrs: nounwind readnone 963define fastcc <256 x double> @vdivswzx_vvsmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 964; CHECK-LABEL: vdivswzx_vvsmvl_imm: 965; CHECK: # %bb.0: 966; CHECK-NEXT: lea %s0, 128 967; CHECK-NEXT: lvl %s0 968; CHECK-NEXT: vdivs.w.zx %v1, %v0, 8, %vm1 969; CHECK-NEXT: lea %s16, 256 970; CHECK-NEXT: lvl %s16 971; CHECK-NEXT: vor %v0, (0)1, %v1 972; CHECK-NEXT: b.l.t (, %s10) 973 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivswzx.vvsmvl(<256 x double> %0, i32 8, <256 x i1> %1, <256 x double> %2, i32 128) 974 ret <256 x double> %4 975} 976 977; Function Attrs: nounwind readnone 978define fastcc <256 x double> @vdivsl_vvvl(<256 x double> %0, <256 x double> %1) { 979; CHECK-LABEL: vdivsl_vvvl: 980; CHECK: # %bb.0: 981; CHECK-NEXT: lea %s0, 256 982; CHECK-NEXT: lvl %s0 983; CHECK-NEXT: vdivs.l %v0, %v0, %v1 984; CHECK-NEXT: b.l.t (, %s10) 985 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivsl.vvvl(<256 x double> %0, <256 x double> %1, i32 256) 986 ret <256 x double> %3 987} 988 989; Function Attrs: nounwind readnone 990declare <256 x double> @llvm.ve.vl.vdivsl.vvvl(<256 x double>, <256 x double>, i32) 991 992; Function Attrs: nounwind readnone 993define fastcc <256 x double> @vdivsl_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { 994; CHECK-LABEL: vdivsl_vvvvl: 995; CHECK: # %bb.0: 996; CHECK-NEXT: lea %s0, 128 997; CHECK-NEXT: lvl %s0 998; CHECK-NEXT: vdivs.l %v2, %v0, %v1 999; CHECK-NEXT: lea %s16, 256 1000; CHECK-NEXT: lvl %s16 1001; CHECK-NEXT: vor %v0, (0)1, %v2 1002; CHECK-NEXT: b.l.t (, %s10) 1003 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivsl.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) 1004 ret <256 x double> %4 1005} 1006 1007; Function Attrs: nounwind readnone 1008declare <256 x double> @llvm.ve.vl.vdivsl.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) 1009 1010; Function Attrs: nounwind readnone 1011define fastcc <256 x double> @vdivsl_vsvl(i64 %0, <256 x double> %1) { 1012; CHECK-LABEL: vdivsl_vsvl: 1013; CHECK: # %bb.0: 1014; CHECK-NEXT: lea %s1, 256 1015; CHECK-NEXT: lvl %s1 1016; CHECK-NEXT: vdivs.l %v0, %s0, %v0 1017; CHECK-NEXT: b.l.t (, %s10) 1018 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivsl.vsvl(i64 %0, <256 x double> %1, i32 256) 1019 ret <256 x double> %3 1020} 1021 1022; Function Attrs: nounwind readnone 1023declare <256 x double> @llvm.ve.vl.vdivsl.vsvl(i64, <256 x double>, i32) 1024 1025; Function Attrs: nounwind readnone 1026define fastcc <256 x double> @vdivsl_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) { 1027; CHECK-LABEL: vdivsl_vsvvl: 1028; CHECK: # %bb.0: 1029; CHECK-NEXT: lea %s1, 128 1030; CHECK-NEXT: lvl %s1 1031; CHECK-NEXT: vdivs.l %v1, %s0, %v0 1032; CHECK-NEXT: lea %s16, 256 1033; CHECK-NEXT: lvl %s16 1034; CHECK-NEXT: vor %v0, (0)1, %v1 1035; CHECK-NEXT: b.l.t (, %s10) 1036 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivsl.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128) 1037 ret <256 x double> %4 1038} 1039 1040; Function Attrs: nounwind readnone 1041declare <256 x double> @llvm.ve.vl.vdivsl.vsvvl(i64, <256 x double>, <256 x double>, i32) 1042 1043; Function Attrs: nounwind readnone 1044define fastcc <256 x double> @vdivsl_vsvl_imm(<256 x double> %0) { 1045; CHECK-LABEL: vdivsl_vsvl_imm: 1046; CHECK: # %bb.0: 1047; CHECK-NEXT: lea %s0, 256 1048; CHECK-NEXT: lvl %s0 1049; CHECK-NEXT: vdivs.l %v0, 8, %v0 1050; CHECK-NEXT: b.l.t (, %s10) 1051 %2 = tail call fast <256 x double> @llvm.ve.vl.vdivsl.vsvl(i64 8, <256 x double> %0, i32 256) 1052 ret <256 x double> %2 1053} 1054 1055; Function Attrs: nounwind readnone 1056define fastcc <256 x double> @vdivsl_vsvvl_imm(<256 x double> %0, <256 x double> %1) { 1057; CHECK-LABEL: vdivsl_vsvvl_imm: 1058; CHECK: # %bb.0: 1059; CHECK-NEXT: lea %s0, 128 1060; CHECK-NEXT: lvl %s0 1061; CHECK-NEXT: vdivs.l %v1, 8, %v0 1062; CHECK-NEXT: lea %s16, 256 1063; CHECK-NEXT: lvl %s16 1064; CHECK-NEXT: vor %v0, (0)1, %v1 1065; CHECK-NEXT: b.l.t (, %s10) 1066 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivsl.vsvvl(i64 8, <256 x double> %0, <256 x double> %1, i32 128) 1067 ret <256 x double> %3 1068} 1069 1070; Function Attrs: nounwind readnone 1071define fastcc <256 x double> @vdivsl_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 1072; CHECK-LABEL: vdivsl_vvvmvl: 1073; CHECK: # %bb.0: 1074; CHECK-NEXT: lea %s0, 128 1075; CHECK-NEXT: lvl %s0 1076; CHECK-NEXT: vdivs.l %v2, %v0, %v1, %vm1 1077; CHECK-NEXT: lea %s16, 256 1078; CHECK-NEXT: lvl %s16 1079; CHECK-NEXT: vor %v0, (0)1, %v2 1080; CHECK-NEXT: b.l.t (, %s10) 1081 %5 = tail call fast <256 x double> @llvm.ve.vl.vdivsl.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 1082 ret <256 x double> %5 1083} 1084 1085; Function Attrs: nounwind readnone 1086declare <256 x double> @llvm.ve.vl.vdivsl.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) 1087 1088; Function Attrs: nounwind readnone 1089define fastcc <256 x double> @vdivsl_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 1090; CHECK-LABEL: vdivsl_vsvmvl: 1091; CHECK: # %bb.0: 1092; CHECK-NEXT: lea %s1, 128 1093; CHECK-NEXT: lvl %s1 1094; CHECK-NEXT: vdivs.l %v1, %s0, %v0, %vm1 1095; CHECK-NEXT: lea %s16, 256 1096; CHECK-NEXT: lvl %s16 1097; CHECK-NEXT: vor %v0, (0)1, %v1 1098; CHECK-NEXT: b.l.t (, %s10) 1099 %5 = tail call fast <256 x double> @llvm.ve.vl.vdivsl.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 1100 ret <256 x double> %5 1101} 1102 1103; Function Attrs: nounwind readnone 1104declare <256 x double> @llvm.ve.vl.vdivsl.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32) 1105 1106; Function Attrs: nounwind readnone 1107define fastcc <256 x double> @vdivsl_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 1108; CHECK-LABEL: vdivsl_vsvmvl_imm: 1109; CHECK: # %bb.0: 1110; CHECK-NEXT: lea %s0, 128 1111; CHECK-NEXT: lvl %s0 1112; CHECK-NEXT: vdivs.l %v1, 8, %v0, %vm1 1113; CHECK-NEXT: lea %s16, 256 1114; CHECK-NEXT: lvl %s16 1115; CHECK-NEXT: vor %v0, (0)1, %v1 1116; CHECK-NEXT: b.l.t (, %s10) 1117 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivsl.vsvmvl(i64 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 1118 ret <256 x double> %4 1119} 1120 1121; Function Attrs: nounwind readnone 1122define fastcc <256 x double> @vdivsl_vvsl(<256 x double> %0, i64 %1) { 1123; CHECK-LABEL: vdivsl_vvsl: 1124; CHECK: # %bb.0: 1125; CHECK-NEXT: lea %s1, 256 1126; CHECK-NEXT: lvl %s1 1127; CHECK-NEXT: vdivs.l %v0, %v0, %s0 1128; CHECK-NEXT: b.l.t (, %s10) 1129 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivsl.vvsl(<256 x double> %0, i64 %1, i32 256) 1130 ret <256 x double> %3 1131} 1132 1133; Function Attrs: nounwind readnone 1134declare <256 x double> @llvm.ve.vl.vdivsl.vvsl(<256 x double>, i64, i32) 1135 1136; Function Attrs: nounwind readnone 1137define fastcc <256 x double> @vdivsl_vvsvl(<256 x double> %0, i64 %1, <256 x double> %2) { 1138; CHECK-LABEL: vdivsl_vvsvl: 1139; CHECK: # %bb.0: 1140; CHECK-NEXT: lea %s1, 128 1141; CHECK-NEXT: lvl %s1 1142; CHECK-NEXT: vdivs.l %v1, %v0, %s0 1143; CHECK-NEXT: lea %s16, 256 1144; CHECK-NEXT: lvl %s16 1145; CHECK-NEXT: vor %v0, (0)1, %v1 1146; CHECK-NEXT: b.l.t (, %s10) 1147 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivsl.vvsvl(<256 x double> %0, i64 %1, <256 x double> %2, i32 128) 1148 ret <256 x double> %4 1149} 1150 1151; Function Attrs: nounwind readnone 1152declare <256 x double> @llvm.ve.vl.vdivsl.vvsvl(<256 x double>, i64, <256 x double>, i32) 1153 1154; Function Attrs: nounwind readnone 1155define fastcc <256 x double> @vdivsl_vvsl_imm(<256 x double> %0) { 1156; CHECK-LABEL: vdivsl_vvsl_imm: 1157; CHECK: # %bb.0: 1158; CHECK-NEXT: lea %s0, 256 1159; CHECK-NEXT: lvl %s0 1160; CHECK-NEXT: vdivs.l %v0, %v0, 8 1161; CHECK-NEXT: b.l.t (, %s10) 1162 %2 = tail call fast <256 x double> @llvm.ve.vl.vdivsl.vvsl(<256 x double> %0, i64 8, i32 256) 1163 ret <256 x double> %2 1164} 1165 1166; Function Attrs: nounwind readnone 1167define fastcc <256 x double> @vdivsl_vvsvl_imm(<256 x double> %0, <256 x double> %1) { 1168; CHECK-LABEL: vdivsl_vvsvl_imm: 1169; CHECK: # %bb.0: 1170; CHECK-NEXT: lea %s0, 128 1171; CHECK-NEXT: lvl %s0 1172; CHECK-NEXT: vdivs.l %v1, %v0, 8 1173; CHECK-NEXT: lea %s16, 256 1174; CHECK-NEXT: lvl %s16 1175; CHECK-NEXT: vor %v0, (0)1, %v1 1176; CHECK-NEXT: b.l.t (, %s10) 1177 %3 = tail call fast <256 x double> @llvm.ve.vl.vdivsl.vvsvl(<256 x double> %0, i64 8, <256 x double> %1, i32 128) 1178 ret <256 x double> %3 1179} 1180 1181; Function Attrs: nounwind readnone 1182define fastcc <256 x double> @vdivsl_vvsmvl(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) { 1183; CHECK-LABEL: vdivsl_vvsmvl: 1184; CHECK: # %bb.0: 1185; CHECK-NEXT: lea %s1, 128 1186; CHECK-NEXT: lvl %s1 1187; CHECK-NEXT: vdivs.l %v1, %v0, %s0, %vm1 1188; CHECK-NEXT: lea %s16, 256 1189; CHECK-NEXT: lvl %s16 1190; CHECK-NEXT: vor %v0, (0)1, %v1 1191; CHECK-NEXT: b.l.t (, %s10) 1192 %5 = tail call fast <256 x double> @llvm.ve.vl.vdivsl.vvsmvl(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3, i32 128) 1193 ret <256 x double> %5 1194} 1195 1196; Function Attrs: nounwind readnone 1197declare <256 x double> @llvm.ve.vl.vdivsl.vvsmvl(<256 x double>, i64, <256 x i1>, <256 x double>, i32) 1198 1199; Function Attrs: nounwind readnone 1200define fastcc <256 x double> @vdivsl_vvsmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 1201; CHECK-LABEL: vdivsl_vvsmvl_imm: 1202; CHECK: # %bb.0: 1203; CHECK-NEXT: lea %s0, 128 1204; CHECK-NEXT: lvl %s0 1205; CHECK-NEXT: vdivs.l %v1, %v0, 8, %vm1 1206; CHECK-NEXT: lea %s16, 256 1207; CHECK-NEXT: lvl %s16 1208; CHECK-NEXT: vor %v0, (0)1, %v1 1209; CHECK-NEXT: b.l.t (, %s10) 1210 %4 = tail call fast <256 x double> @llvm.ve.vl.vdivsl.vvsmvl(<256 x double> %0, i64 8, <256 x i1> %1, <256 x double> %2, i32 128) 1211 ret <256 x double> %4 1212} 1213