1; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s 2 3; This tests that indirectbr instructions are lowered to switches. Currently we 4; just re-use the IndirectBrExpand Pass; it has its own IR-level test. 5; So this test just ensures that the pass gets run and we can lower indirectbr 6 7target triple = "wasm32" 8 9@test1.targets = constant [4 x i8*] [i8* blockaddress(@test1, %bb0), 10 i8* blockaddress(@test1, %bb1), 11 i8* blockaddress(@test1, %bb2), 12 i8* blockaddress(@test1, %bb3)] 13 14; Just check the barest skeleton of the structure 15; CHECK-LABEL: test1: 16; CHECK: i32.load 17; CHECK: i32.load 18; CHECK: loop 19; CHECK: block 20; CHECK: block 21; CHECK: block 22; CHECK: block 23; CHECK: br_table ${{[^,]+}}, 1, 2, 0 24; CHECK: end_block 25; CHECK: end_block 26; CHECK: end_block 27; CHECK: end_block 28; CHECK: br 29; CHECK: end_loop 30; CHECK: end_function 31; CHECK: test1.targets: 32; CHECK-NEXT: .int32 33; CHECK-NEXT: .int32 34; CHECK-NEXT: .int32 35; CHECK-NEXT: .int32 36 37define void @test1(i32* readonly %p, i32* %sink) #0 { 38 39entry: 40 %i0 = load i32, i32* %p 41 %target.i0 = getelementptr [4 x i8*], [4 x i8*]* @test1.targets, i32 0, i32 %i0 42 %target0 = load i8*, i8** %target.i0 43 ; Only a subset of blocks are viable successors here. 44 indirectbr i8* %target0, [label %bb0, label %bb1] 45 46 47bb0: 48 store volatile i32 0, i32* %sink 49 br label %latch 50 51bb1: 52 store volatile i32 1, i32* %sink 53 br label %latch 54 55bb2: 56 store volatile i32 2, i32* %sink 57 br label %latch 58 59bb3: 60 store volatile i32 3, i32* %sink 61 br label %latch 62 63latch: 64 %i.next = load i32, i32* %p 65 %target.i.next = getelementptr [4 x i8*], [4 x i8*]* @test1.targets, i32 0, i32 %i.next 66 %target.next = load i8*, i8** %target.i.next 67 ; A different subset of blocks are viable successors here. 68 indirectbr i8* %target.next, [label %bb1, label %bb2] 69} 70