1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128 2; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128 3 4; Test that SIMD128 intrinsics lower as expected. These intrinsics are 5; only expected to lower successfully if the simd128 attribute is 6; enabled and legal types are used. 7 8target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" 9target triple = "wasm32-unknown-unknown" 10 11; ============================================================================== 12; 16 x i8 13; ============================================================================== 14; CHECK-LABEL: swizzle_v16i8: 15; SIMD128-NEXT: .functype swizzle_v16i8 (v128, v128) -> (v128){{$}} 16; SIMD128-NEXT: v8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}} 17; SIMD128-NEXT: return $pop[[R]]{{$}} 18declare <16 x i8> @llvm.wasm.swizzle(<16 x i8>, <16 x i8>) 19define <16 x i8> @swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) { 20 %a = call <16 x i8> @llvm.wasm.swizzle(<16 x i8> %x, <16 x i8> %y) 21 ret <16 x i8> %a 22} 23 24; CHECK-LABEL: add_sat_s_v16i8: 25; SIMD128-NEXT: .functype add_sat_s_v16i8 (v128, v128) -> (v128){{$}} 26; SIMD128-NEXT: i8x16.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}} 27; SIMD128-NEXT: return $pop[[R]]{{$}} 28declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>) 29define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 30 %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) 31 ret <16 x i8> %a 32} 33 34; CHECK-LABEL: add_sat_u_v16i8: 35; SIMD128-NEXT: .functype add_sat_u_v16i8 (v128, v128) -> (v128){{$}} 36; SIMD128-NEXT: i8x16.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}} 37; SIMD128-NEXT: return $pop[[R]]{{$}} 38declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) 39define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 40 %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) 41 ret <16 x i8> %a 42} 43 44; CHECK-LABEL: sub_sat_s_v16i8: 45; SIMD128-NEXT: .functype sub_sat_s_v16i8 (v128, v128) -> (v128){{$}} 46; SIMD128-NEXT: i8x16.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}} 47; SIMD128-NEXT: return $pop[[R]]{{$}} 48declare <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8(<16 x i8>, <16 x i8>) 49define <16 x i8> @sub_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 50 %a = call <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8( 51 <16 x i8> %x, <16 x i8> %y 52 ) 53 ret <16 x i8> %a 54} 55 56; CHECK-LABEL: sub_sat_u_v16i8: 57; SIMD128-NEXT: .functype sub_sat_u_v16i8 (v128, v128) -> (v128){{$}} 58; SIMD128-NEXT: i8x16.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}} 59; SIMD128-NEXT: return $pop[[R]]{{$}} 60declare <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8(<16 x i8>, <16 x i8>) 61define <16 x i8> @sub_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 62 %a = call <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8( 63 <16 x i8> %x, <16 x i8> %y 64 ) 65 ret <16 x i8> %a 66} 67 68; CHECK-LABEL: avgr_u_v16i8: 69; SIMD128-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}} 70; SIMD128-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 71; SIMD128-NEXT: return $pop[[R]]{{$}} 72declare <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8>, <16 x i8>) 73define <16 x i8> @avgr_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 74 %a = call <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8> %x, <16 x i8> %y) 75 ret <16 x i8> %a 76} 77 78; CHECK-LABEL: popcnt_v16i8: 79; SIMD128-NEXT: .functype popcnt_v16i8 (v128) -> (v128){{$}} 80; SIMD128-NEXT: i8x16.popcnt $push[[R:[0-9]+]]=, $0{{$}} 81; SIMD128-NEXT: return $pop[[R]]{{$}} 82declare <16 x i8> @llvm.wasm.popcnt(<16 x i8>) 83define <16 x i8> @popcnt_v16i8(<16 x i8> %x) { 84 %a = call <16 x i8> @llvm.wasm.popcnt(<16 x i8> %x) 85 ret <16 x i8> %a 86} 87 88; CHECK-LABEL: any_v16i8: 89; SIMD128-NEXT: .functype any_v16i8 (v128) -> (i32){{$}} 90; SIMD128-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}} 91; SIMD128-NEXT: return $pop[[R]]{{$}} 92declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>) 93define i32 @any_v16i8(<16 x i8> %x) { 94 %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x) 95 ret i32 %a 96} 97 98; CHECK-LABEL: all_v16i8: 99; SIMD128-NEXT: .functype all_v16i8 (v128) -> (i32){{$}} 100; SIMD128-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}} 101; SIMD128-NEXT: return $pop[[R]]{{$}} 102declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>) 103define i32 @all_v16i8(<16 x i8> %x) { 104 %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x) 105 ret i32 %a 106} 107 108; CHECK-LABEL: bitmask_v16i8: 109; SIMD128-NEXT: .functype bitmask_v16i8 (v128) -> (i32){{$}} 110; SIMD128-NEXT: i8x16.bitmask $push[[R:[0-9]+]]=, $0{{$}} 111; SIMD128-NEXT: return $pop[[R]]{{$}} 112declare i32 @llvm.wasm.bitmask.v16i8(<16 x i8>) 113define i32 @bitmask_v16i8(<16 x i8> %x) { 114 %a = call i32 @llvm.wasm.bitmask.v16i8(<16 x i8> %x) 115 ret i32 %a 116} 117 118; CHECK-LABEL: bitselect_v16i8: 119; SIMD128-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}} 120; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 121; SIMD128-NEXT: return $pop[[R]]{{$}} 122declare <16 x i8> @llvm.wasm.bitselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) 123define <16 x i8> @bitselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) { 124 %a = call <16 x i8> @llvm.wasm.bitselect.v16i8( 125 <16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c 126 ) 127 ret <16 x i8> %a 128} 129 130; CHECK-LABEL: signselect_v16i8: 131; SIMD128-NEXT: .functype signselect_v16i8 (v128, v128, v128) -> (v128){{$}} 132; SIMD128-NEXT: i8x16.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 133; SIMD128-NEXT: return $pop[[R]]{{$}} 134declare <16 x i8> @llvm.wasm.signselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) 135define <16 x i8> @signselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) { 136 %a = call <16 x i8> @llvm.wasm.signselect.v16i8( 137 <16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c 138 ) 139 ret <16 x i8> %a 140} 141 142; CHECK-LABEL: narrow_signed_v16i8: 143; SIMD128-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}} 144; SIMD128-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 145; SIMD128-NEXT: return $pop[[R]]{{$}} 146declare <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(<8 x i16>, <8 x i16>) 147define <16 x i8> @narrow_signed_v16i8(<8 x i16> %low, <8 x i16> %high) { 148 %a = call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16( 149 <8 x i16> %low, <8 x i16> %high 150 ) 151 ret <16 x i8> %a 152} 153 154; CHECK-LABEL: narrow_unsigned_v16i8: 155; SIMD128-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}} 156; SIMD128-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}} 157; SIMD128-NEXT: return $pop[[R]]{{$}} 158declare <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(<8 x i16>, <8 x i16>) 159define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) { 160 %a = call <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16( 161 <8 x i16> %low, <8 x i16> %high 162 ) 163 ret <16 x i8> %a 164} 165 166; CHECK-LABEL: shuffle_v16i8: 167; NO-SIMD128-NOT: v8x16 168; SIMD128-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}} 169; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1, 170; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}} 171; SIMD128-NEXT: return $pop[[R]]{{$}} 172declare <16 x i8> @llvm.wasm.shuffle( 173 <16 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, 174 i32, i32, i32, i32, i32) 175define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) { 176 %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y, 177 i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, 178 i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 35) 179 ret <16 x i8> %res 180} 181 182; CHECK-LABEL: shuffle_undef_v16i8: 183; NO-SIMD128-NOT: v8x16 184; SIMD128-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}} 185; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1, 186; SIMD128-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2{{$}} 187; SIMD128-NEXT: return $pop[[R]]{{$}} 188define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) { 189 %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y, 190 i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, 191 i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, 192 i32 undef, i32 undef, i32 undef, i32 2) 193 ret <16 x i8> %res 194} 195 196; ============================================================================== 197; 8 x i16 198; ============================================================================== 199; CHECK-LABEL: add_sat_s_v8i16: 200; SIMD128-NEXT: .functype add_sat_s_v8i16 (v128, v128) -> (v128){{$}} 201; SIMD128-NEXT: i16x8.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}} 202; SIMD128-NEXT: return $pop[[R]]{{$}} 203declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) 204define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 205 %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) 206 ret <8 x i16> %a 207} 208 209; CHECK-LABEL: add_sat_u_v8i16: 210; SIMD128-NEXT: .functype add_sat_u_v8i16 (v128, v128) -> (v128){{$}} 211; SIMD128-NEXT: i16x8.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}} 212; SIMD128-NEXT: return $pop[[R]]{{$}} 213declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>) 214define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 215 %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) 216 ret <8 x i16> %a 217} 218 219; CHECK-LABEL: sub_sat_s_v8i16: 220; SIMD128-NEXT: .functype sub_sat_s_v8i16 (v128, v128) -> (v128){{$}} 221; SIMD128-NEXT: i16x8.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}} 222; SIMD128-NEXT: return $pop[[R]]{{$}} 223declare <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16(<8 x i16>, <8 x i16>) 224define <8 x i16> @sub_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 225 %a = call <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16( 226 <8 x i16> %x, <8 x i16> %y 227 ) 228 ret <8 x i16> %a 229} 230 231; CHECK-LABEL: sub_sat_u_v8i16: 232; SIMD128-NEXT: .functype sub_sat_u_v8i16 (v128, v128) -> (v128){{$}} 233; SIMD128-NEXT: i16x8.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}} 234; SIMD128-NEXT: return $pop[[R]]{{$}} 235declare <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16(<8 x i16>, <8 x i16>) 236define <8 x i16> @sub_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 237 %a = call <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16( 238 <8 x i16> %x, <8 x i16> %y 239 ) 240 ret <8 x i16> %a 241} 242 243; CHECK-LABEL: avgr_u_v8i16: 244; SIMD128-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}} 245; SIMD128-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 246; SIMD128-NEXT: return $pop[[R]]{{$}} 247declare <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16>, <8 x i16>) 248define <8 x i16> @avgr_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 249 %a = call <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16> %x, <8 x i16> %y) 250 ret <8 x i16> %a 251} 252 253; CHECK-LABEL: q15mulr_sat_s_v8i16: 254; SIMD128-NEXT: .functype q15mulr_sat_s_v8i16 (v128, v128) -> (v128){{$}} 255; SIMD128-NEXT: i16x8.q15mulr_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 256; SIMD128-NEXT: return $pop[[R]]{{$}} 257declare <8 x i16> @llvm.wasm.q15mulr.saturate.signed(<8 x i16>, <8 x i16>) 258define <8 x i16> @q15mulr_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 259 %a = call <8 x i16> @llvm.wasm.q15mulr.saturate.signed(<8 x i16> %x, 260 <8 x i16> %y) 261 ret <8 x i16> %a 262} 263 264; CHECK-LABEL: extmul_low_s_v8i16: 265; SIMD128-NEXT: .functype extmul_low_s_v8i16 (v128, v128) -> (v128){{$}} 266; SIMD128-NEXT: i16x8.extmul_low_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}} 267; SIMD128-NEXT: return $pop[[R]]{{$}} 268declare <8 x i16> @llvm.wasm.extmul.low.signed.v8i16(<16 x i8>, <16 x i8>) 269define <8 x i16> @extmul_low_s_v8i16(<16 x i8> %x, <16 x i8> %y) { 270 %a = call <8 x i16> @llvm.wasm.extmul.low.signed.v8i16( 271 <16 x i8> %x, <16 x i8> %y 272 ) 273 ret <8 x i16> %a 274} 275 276; CHECK-LABEL: extmul_high_s_v8i16: 277; SIMD128-NEXT: .functype extmul_high_s_v8i16 (v128, v128) -> (v128){{$}} 278; SIMD128-NEXT: i16x8.extmul_high_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}} 279; SIMD128-NEXT: return $pop[[R]]{{$}} 280declare <8 x i16> @llvm.wasm.extmul.high.signed.v8i16(<16 x i8>, <16 x i8>) 281define <8 x i16> @extmul_high_s_v8i16(<16 x i8> %x, <16 x i8> %y) { 282 %a = call <8 x i16> @llvm.wasm.extmul.high.signed.v8i16( 283 <16 x i8> %x, <16 x i8> %y 284 ) 285 ret <8 x i16> %a 286} 287 288; CHECK-LABEL: extmul_low_u_v8i16: 289; SIMD128-NEXT: .functype extmul_low_u_v8i16 (v128, v128) -> (v128){{$}} 290; SIMD128-NEXT: i16x8.extmul_low_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}} 291; SIMD128-NEXT: return $pop[[R]]{{$}} 292declare <8 x i16> @llvm.wasm.extmul.low.unsigned.v8i16(<16 x i8>, <16 x i8>) 293define <8 x i16> @extmul_low_u_v8i16(<16 x i8> %x, <16 x i8> %y) { 294 %a = call <8 x i16> @llvm.wasm.extmul.low.unsigned.v8i16( 295 <16 x i8> %x, <16 x i8> %y 296 ) 297 ret <8 x i16> %a 298} 299 300; CHECK-LABEL: extmul_high_u_v8i16: 301; SIMD128-NEXT: .functype extmul_high_u_v8i16 (v128, v128) -> (v128){{$}} 302; SIMD128-NEXT: i16x8.extmul_high_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}} 303; SIMD128-NEXT: return $pop[[R]]{{$}} 304declare <8 x i16> @llvm.wasm.extmul.high.unsigned.v8i16(<16 x i8>, <16 x i8>) 305define <8 x i16> @extmul_high_u_v8i16(<16 x i8> %x, <16 x i8> %y) { 306 %a = call <8 x i16> @llvm.wasm.extmul.high.unsigned.v8i16( 307 <16 x i8> %x, <16 x i8> %y 308 ) 309 ret <8 x i16> %a 310} 311 312; CHECK-LABEL: any_v8i16: 313; SIMD128-NEXT: .functype any_v8i16 (v128) -> (i32){{$}} 314; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}} 315; SIMD128-NEXT: return $pop[[R]]{{$}} 316declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>) 317define i32 @any_v8i16(<8 x i16> %x) { 318 %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x) 319 ret i32 %a 320} 321 322; CHECK-LABEL: all_v8i16: 323; SIMD128-NEXT: .functype all_v8i16 (v128) -> (i32){{$}} 324; SIMD128-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}} 325; SIMD128-NEXT: return $pop[[R]]{{$}} 326declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>) 327define i32 @all_v8i16(<8 x i16> %x) { 328 %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x) 329 ret i32 %a 330} 331 332; CHECK-LABEL: bitmask_v8i16: 333; SIMD128-NEXT: .functype bitmask_v8i16 (v128) -> (i32){{$}} 334; SIMD128-NEXT: i16x8.bitmask $push[[R:[0-9]+]]=, $0{{$}} 335; SIMD128-NEXT: return $pop[[R]]{{$}} 336declare i32 @llvm.wasm.bitmask.v8i16(<8 x i16>) 337define i32 @bitmask_v8i16(<8 x i16> %x) { 338 %a = call i32 @llvm.wasm.bitmask.v8i16(<8 x i16> %x) 339 ret i32 %a 340} 341 342; CHECK-LABEL: bitselect_v8i16: 343; SIMD128-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}} 344; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 345; SIMD128-NEXT: return $pop[[R]]{{$}} 346declare <8 x i16> @llvm.wasm.bitselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) 347define <8 x i16> @bitselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) { 348 %a = call <8 x i16> @llvm.wasm.bitselect.v8i16( 349 <8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c 350 ) 351 ret <8 x i16> %a 352} 353 354; CHECK-LABEL: signselect_v8i16: 355; SIMD128-NEXT: .functype signselect_v8i16 (v128, v128, v128) -> (v128){{$}} 356; SIMD128-NEXT: i16x8.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 357; SIMD128-NEXT: return $pop[[R]]{{$}} 358declare <8 x i16> @llvm.wasm.signselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) 359define <8 x i16> @signselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) { 360 %a = call <8 x i16> @llvm.wasm.signselect.v8i16( 361 <8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c 362 ) 363 ret <8 x i16> %a 364} 365 366; CHECK-LABEL: narrow_signed_v8i16: 367; SIMD128-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}} 368; SIMD128-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}} 369; SIMD128-NEXT: return $pop[[R]]{{$}} 370declare <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(<4 x i32>, <4 x i32>) 371define <8 x i16> @narrow_signed_v8i16(<4 x i32> %low, <4 x i32> %high) { 372 %a = call <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32( 373 <4 x i32> %low, <4 x i32> %high 374 ) 375 ret <8 x i16> %a 376} 377 378; CHECK-LABEL: narrow_unsigned_v8i16: 379; SIMD128-NEXT: .functype narrow_unsigned_v8i16 (v128, v128) -> (v128){{$}} 380; SIMD128-NEXT: i16x8.narrow_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}} 381; SIMD128-NEXT: return $pop[[R]]{{$}} 382declare <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(<4 x i32>, <4 x i32>) 383define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) { 384 %a = call <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32( 385 <4 x i32> %low, <4 x i32> %high 386 ) 387 ret <8 x i16> %a 388} 389 390; ============================================================================== 391; 4 x i32 392; ============================================================================== 393; CHECK-LABEL: dot: 394; SIMD128-NEXT: .functype dot (v128, v128) -> (v128){{$}} 395; SIMD128-NEXT: i32x4.dot_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 396; SIMD128-NEXT: return $pop[[R]]{{$}} 397declare <4 x i32> @llvm.wasm.dot(<8 x i16>, <8 x i16>) 398define <4 x i32> @dot(<8 x i16> %x, <8 x i16> %y) { 399 %a = call <4 x i32> @llvm.wasm.dot(<8 x i16> %x, <8 x i16> %y) 400 ret <4 x i32> %a 401} 402 403 404; CHECK-LABEL: extmul_low_s_v4i32: 405; SIMD128-NEXT: .functype extmul_low_s_v4i32 (v128, v128) -> (v128){{$}} 406; SIMD128-NEXT: i32x4.extmul_low_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 407; SIMD128-NEXT: return $pop[[R]]{{$}} 408declare <4 x i32> @llvm.wasm.extmul.low.signed.v4i32(<8 x i16>, <8 x i16>) 409define <4 x i32> @extmul_low_s_v4i32(<8 x i16> %x, <8 x i16> %y) { 410 %a = call <4 x i32> @llvm.wasm.extmul.low.signed.v4i32( 411 <8 x i16> %x, <8 x i16> %y 412 ) 413 ret <4 x i32> %a 414} 415 416; CHECK-LABEL: extmul_high_s_v4i32: 417; SIMD128-NEXT: .functype extmul_high_s_v4i32 (v128, v128) -> (v128){{$}} 418; SIMD128-NEXT: i32x4.extmul_high_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 419; SIMD128-NEXT: return $pop[[R]]{{$}} 420declare <4 x i32> @llvm.wasm.extmul.high.signed.v4i32(<8 x i16>, <8 x i16>) 421define <4 x i32> @extmul_high_s_v4i32(<8 x i16> %x, <8 x i16> %y) { 422 %a = call <4 x i32> @llvm.wasm.extmul.high.signed.v4i32( 423 <8 x i16> %x, <8 x i16> %y 424 ) 425 ret <4 x i32> %a 426} 427 428; CHECK-LABEL: extmul_low_u_v4i32: 429; SIMD128-NEXT: .functype extmul_low_u_v4i32 (v128, v128) -> (v128){{$}} 430; SIMD128-NEXT: i32x4.extmul_low_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}} 431; SIMD128-NEXT: return $pop[[R]]{{$}} 432declare <4 x i32> @llvm.wasm.extmul.low.unsigned.v4i32(<8 x i16>, <8 x i16>) 433define <4 x i32> @extmul_low_u_v4i32(<8 x i16> %x, <8 x i16> %y) { 434 %a = call <4 x i32> @llvm.wasm.extmul.low.unsigned.v4i32( 435 <8 x i16> %x, <8 x i16> %y 436 ) 437 ret <4 x i32> %a 438} 439 440; CHECK-LABEL: extmul_high_u_v4i32: 441; SIMD128-NEXT: .functype extmul_high_u_v4i32 (v128, v128) -> (v128){{$}} 442; SIMD128-NEXT: i32x4.extmul_high_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}} 443; SIMD128-NEXT: return $pop[[R]]{{$}} 444declare <4 x i32> @llvm.wasm.extmul.high.unsigned.v4i32(<8 x i16>, <8 x i16>) 445define <4 x i32> @extmul_high_u_v4i32(<8 x i16> %x, <8 x i16> %y) { 446 %a = call <4 x i32> @llvm.wasm.extmul.high.unsigned.v4i32( 447 <8 x i16> %x, <8 x i16> %y 448 ) 449 ret <4 x i32> %a 450} 451 452; CHECK-LABEL: any_v4i32: 453; SIMD128-NEXT: .functype any_v4i32 (v128) -> (i32){{$}} 454; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}} 455; SIMD128-NEXT: return $pop[[R]]{{$}} 456declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>) 457define i32 @any_v4i32(<4 x i32> %x) { 458 %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x) 459 ret i32 %a 460} 461 462; CHECK-LABEL: all_v4i32: 463; SIMD128-NEXT: .functype all_v4i32 (v128) -> (i32){{$}} 464; SIMD128-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}} 465; SIMD128-NEXT: return $pop[[R]]{{$}} 466declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>) 467define i32 @all_v4i32(<4 x i32> %x) { 468 %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x) 469 ret i32 %a 470} 471 472; CHECK-LABEL: bitmask_v4i32: 473; SIMD128-NEXT: .functype bitmask_v4i32 (v128) -> (i32){{$}} 474; SIMD128-NEXT: i32x4.bitmask $push[[R:[0-9]+]]=, $0{{$}} 475; SIMD128-NEXT: return $pop[[R]]{{$}} 476declare i32 @llvm.wasm.bitmask.v4i32(<4 x i32>) 477define i32 @bitmask_v4i32(<4 x i32> %x) { 478 %a = call i32 @llvm.wasm.bitmask.v4i32(<4 x i32> %x) 479 ret i32 %a 480} 481 482; CHECK-LABEL: bitselect_v4i32: 483; SIMD128-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}} 484; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 485; SIMD128-NEXT: return $pop[[R]]{{$}} 486declare <4 x i32> @llvm.wasm.bitselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 487define <4 x i32> @bitselect_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c) { 488 %a = call <4 x i32> @llvm.wasm.bitselect.v4i32( 489 <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c 490 ) 491 ret <4 x i32> %a 492} 493 494; CHECK-LABEL: signselect_v4i32: 495; SIMD128-NEXT: .functype signselect_v4i32 (v128, v128, v128) -> (v128){{$}} 496; SIMD128-NEXT: i32x4.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 497; SIMD128-NEXT: return $pop[[R]]{{$}} 498declare <4 x i32> @llvm.wasm.signselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 499define <4 x i32> @signselect_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c) { 500 %a = call <4 x i32> @llvm.wasm.signselect.v4i32( 501 <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c 502 ) 503 ret <4 x i32> %a 504} 505 506; CHECK-LABEL: trunc_sat_s_v4i32: 507; NO-SIMD128-NOT: f32x4 508; SIMD128-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}} 509; SIMD128-NEXT: i32x4.trunc_sat_f32x4_s $push[[R:[0-9]+]]=, $0 510; SIMD128-NEXT: return $pop[[R]] 511declare <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float>) 512define <4 x i32> @trunc_sat_s_v4i32(<4 x float> %x) { 513 %a = call <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float> %x) 514 ret <4 x i32> %a 515} 516 517; CHECK-LABEL: trunc_sat_u_v4i32: 518; NO-SIMD128-NOT: f32x4 519; SIMD128-NEXT: .functype trunc_sat_u_v4i32 (v128) -> (v128){{$}} 520; SIMD128-NEXT: i32x4.trunc_sat_f32x4_u $push[[R:[0-9]+]]=, $0 521; SIMD128-NEXT: return $pop[[R]] 522declare <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float>) 523define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) { 524 %a = call <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float> %x) 525 ret <4 x i32> %a 526} 527 528; ============================================================================== 529; 2 x i64 530; ============================================================================== 531; CHECK-LABEL: eq_v2i64: 532; SIMD128-NEXT: .functype eq_v2i64 (v128, v128) -> (v128){{$}} 533; SIMD128-NEXT: i64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}} 534; SIMD128-NEXT: return $pop[[R]]{{$}} 535declare <2 x i64> @llvm.wasm.eq(<2 x i64>, <2 x i64>) 536define <2 x i64> @eq_v2i64(<2 x i64> %x, <2 x i64> %y) { 537 %a = call <2 x i64> @llvm.wasm.eq(<2 x i64> %x, <2 x i64> %y) 538 ret <2 x i64> %a 539} 540 541; CHECK-LABEL: widen_low_s_v2i64: 542; SIMD128-NEXT: .functype widen_low_s_v2i64 (v128) -> (v128){{$}} 543; SIMD128-NEXT: i64x2.widen_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}} 544; SIMD128-NEXT: return $pop[[R]]{{$}} 545declare <2 x i64> @llvm.wasm.widen.low.signed(<4 x i32>) 546define <2 x i64> @widen_low_s_v2i64(<4 x i32> %x) { 547 %a = call <2 x i64> @llvm.wasm.widen.low.signed(<4 x i32> %x) 548 ret <2 x i64> %a 549} 550 551; CHECK-LABEL: widen_high_s_v2i64: 552; SIMD128-NEXT: .functype widen_high_s_v2i64 (v128) -> (v128){{$}} 553; SIMD128-NEXT: i64x2.widen_high_i32x4_s $push[[R:[0-9]+]]=, $0{{$}} 554; SIMD128-NEXT: return $pop[[R]]{{$}} 555declare <2 x i64> @llvm.wasm.widen.high.signed(<4 x i32>) 556define <2 x i64> @widen_high_s_v2i64(<4 x i32> %x) { 557 %a = call <2 x i64> @llvm.wasm.widen.high.signed(<4 x i32> %x) 558 ret <2 x i64> %a 559} 560 561; CHECK-LABEL: widen_low_u_v2i64: 562; SIMD128-NEXT: .functype widen_low_u_v2i64 (v128) -> (v128){{$}} 563; SIMD128-NEXT: i64x2.widen_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}} 564; SIMD128-NEXT: return $pop[[R]]{{$}} 565declare <2 x i64> @llvm.wasm.widen.low.unsigned(<4 x i32>) 566define <2 x i64> @widen_low_u_v2i64(<4 x i32> %x) { 567 %a = call <2 x i64> @llvm.wasm.widen.low.unsigned(<4 x i32> %x) 568 ret <2 x i64> %a 569} 570 571; CHECK-LABEL: widen_high_u_v2i64: 572; SIMD128-NEXT: .functype widen_high_u_v2i64 (v128) -> (v128){{$}} 573; SIMD128-NEXT: i64x2.widen_high_i32x4_u $push[[R:[0-9]+]]=, $0{{$}} 574; SIMD128-NEXT: return $pop[[R]]{{$}} 575declare <2 x i64> @llvm.wasm.widen.high.unsigned(<4 x i32>) 576define <2 x i64> @widen_high_u_v2i64(<4 x i32> %x) { 577 %a = call <2 x i64> @llvm.wasm.widen.high.unsigned(<4 x i32> %x) 578 ret <2 x i64> %a 579} 580 581; CHECK-LABEL: extmul_low_s_v2i64: 582; SIMD128-NEXT: .functype extmul_low_s_v2i64 (v128, v128) -> (v128){{$}} 583; SIMD128-NEXT: i64x2.extmul_low_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}} 584; SIMD128-NEXT: return $pop[[R]]{{$}} 585declare <2 x i64> @llvm.wasm.extmul.low.signed.v2i64(<4 x i32>, <4 x i32>) 586define <2 x i64> @extmul_low_s_v2i64(<4 x i32> %x, <4 x i32> %y) { 587 %a = call <2 x i64> @llvm.wasm.extmul.low.signed.v2i64( 588 <4 x i32> %x, <4 x i32> %y 589 ) 590 ret <2 x i64> %a 591} 592 593; CHECK-LABEL: extmul_high_s_v2i64: 594; SIMD128-NEXT: .functype extmul_high_s_v2i64 (v128, v128) -> (v128){{$}} 595; SIMD128-NEXT: i64x2.extmul_high_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}} 596; SIMD128-NEXT: return $pop[[R]]{{$}} 597declare <2 x i64> @llvm.wasm.extmul.high.signed.v2i64(<4 x i32>, <4 x i32>) 598define <2 x i64> @extmul_high_s_v2i64(<4 x i32> %x, <4 x i32> %y) { 599 %a = call <2 x i64> @llvm.wasm.extmul.high.signed.v2i64( 600 <4 x i32> %x, <4 x i32> %y 601 ) 602 ret <2 x i64> %a 603} 604 605; CHECK-LABEL: extmul_low_u_v2i64: 606; SIMD128-NEXT: .functype extmul_low_u_v2i64 (v128, v128) -> (v128){{$}} 607; SIMD128-NEXT: i64x2.extmul_low_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}} 608; SIMD128-NEXT: return $pop[[R]]{{$}} 609declare <2 x i64> @llvm.wasm.extmul.low.unsigned.v2i64(<4 x i32>, <4 x i32>) 610define <2 x i64> @extmul_low_u_v2i64(<4 x i32> %x, <4 x i32> %y) { 611 %a = call <2 x i64> @llvm.wasm.extmul.low.unsigned.v2i64( 612 <4 x i32> %x, <4 x i32> %y 613 ) 614 ret <2 x i64> %a 615} 616 617; CHECK-LABEL: extmul_high_u_v2i64: 618; SIMD128-NEXT: .functype extmul_high_u_v2i64 (v128, v128) -> (v128){{$}} 619; SIMD128-NEXT: i64x2.extmul_high_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}} 620; SIMD128-NEXT: return $pop[[R]]{{$}} 621declare <2 x i64> @llvm.wasm.extmul.high.unsigned.v2i64(<4 x i32>, <4 x i32>) 622define <2 x i64> @extmul_high_u_v2i64(<4 x i32> %x, <4 x i32> %y) { 623 %a = call <2 x i64> @llvm.wasm.extmul.high.unsigned.v2i64( 624 <4 x i32> %x, <4 x i32> %y 625 ) 626 ret <2 x i64> %a 627} 628 629; CHECK-LABEL: any_v2i64: 630; SIMD128-NEXT: .functype any_v2i64 (v128) -> (i32){{$}} 631; SIMD128-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}} 632; SIMD128-NEXT: return $pop[[R]]{{$}} 633declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>) 634define i32 @any_v2i64(<2 x i64> %x) { 635 %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x) 636 ret i32 %a 637} 638 639; CHECK-LABEL: all_v2i64: 640; SIMD128-NEXT: .functype all_v2i64 (v128) -> (i32){{$}} 641; SIMD128-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}} 642; SIMD128-NEXT: return $pop[[R]]{{$}} 643declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>) 644define i32 @all_v2i64(<2 x i64> %x) { 645 %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x) 646 ret i32 %a 647} 648 649; CHECK-LABEL: bitmask_v2i64: 650; SIMD128-NEXT: .functype bitmask_v2i64 (v128) -> (i32){{$}} 651; SIMD128-NEXT: i64x2.bitmask $push[[R:[0-9]+]]=, $0{{$}} 652; SIMD128-NEXT: return $pop[[R]]{{$}} 653declare i32 @llvm.wasm.bitmask.v2i64(<2 x i64>) 654define i32 @bitmask_v2i64(<2 x i64> %x) { 655 %a = call i32 @llvm.wasm.bitmask.v2i64(<2 x i64> %x) 656 ret i32 %a 657} 658 659; CHECK-LABEL: bitselect_v2i64: 660; SIMD128-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}} 661; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 662; SIMD128-NEXT: return $pop[[R]]{{$}} 663declare <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) 664define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) { 665 %a = call <2 x i64> @llvm.wasm.bitselect.v2i64( 666 <2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c 667 ) 668 ret <2 x i64> %a 669} 670 671; CHECK-LABEL: signselect_v2i64: 672; SIMD128-NEXT: .functype signselect_v2i64 (v128, v128, v128) -> (v128){{$}} 673; SIMD128-NEXT: i64x2.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 674; SIMD128-NEXT: return $pop[[R]]{{$}} 675declare <2 x i64> @llvm.wasm.signselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) 676define <2 x i64> @signselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) { 677 %a = call <2 x i64> @llvm.wasm.signselect.v2i64( 678 <2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c 679 ) 680 ret <2 x i64> %a 681} 682 683; ============================================================================== 684; 4 x f32 685; ============================================================================== 686; CHECK-LABEL: bitselect_v4f32: 687; SIMD128-NEXT: .functype bitselect_v4f32 (v128, v128, v128) -> (v128){{$}} 688; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 689; SIMD128-NEXT: return $pop[[R]]{{$}} 690declare <4 x float> @llvm.wasm.bitselect.v4f32(<4 x float>, <4 x float>, <4 x float>) 691define <4 x float> @bitselect_v4f32(<4 x float> %v1, <4 x float> %v2, <4 x float> %c) { 692 %a = call <4 x float> @llvm.wasm.bitselect.v4f32( 693 <4 x float> %v1, <4 x float> %v2, <4 x float> %c 694 ) 695 ret <4 x float> %a 696} 697 698; CHECK-LABEL: pmin_v4f32: 699; SIMD128-NEXT: .functype pmin_v4f32 (v128, v128) -> (v128){{$}} 700; SIMD128-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 701; SIMD128-NEXT: return $pop[[R]]{{$}} 702declare <4 x float> @llvm.wasm.pmin.v4f32(<4 x float>, <4 x float>) 703define <4 x float> @pmin_v4f32(<4 x float> %a, <4 x float> %b) { 704 %v = call <4 x float> @llvm.wasm.pmin.v4f32(<4 x float> %a, <4 x float> %b) 705 ret <4 x float> %v 706} 707 708; CHECK-LABEL: pmax_v4f32: 709; SIMD128-NEXT: .functype pmax_v4f32 (v128, v128) -> (v128){{$}} 710; SIMD128-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 711; SIMD128-NEXT: return $pop[[R]]{{$}} 712declare <4 x float> @llvm.wasm.pmax.v4f32(<4 x float>, <4 x float>) 713define <4 x float> @pmax_v4f32(<4 x float> %a, <4 x float> %b) { 714 %v = call <4 x float> @llvm.wasm.pmax.v4f32(<4 x float> %a, <4 x float> %b) 715 ret <4 x float> %v 716} 717 718; CHECK-LABEL: ceil_v4f32: 719; SIMD128-NEXT: .functype ceil_v4f32 (v128) -> (v128){{$}} 720; SIMD128-NEXT: f32x4.ceil $push[[R:[0-9]+]]=, $0{{$}} 721; SIMD128-NEXT: return $pop[[R]]{{$}} 722declare <4 x float> @llvm.wasm.ceil.v4f32(<4 x float>) 723define <4 x float> @ceil_v4f32(<4 x float> %a) { 724 %v = call <4 x float> @llvm.wasm.ceil.v4f32(<4 x float> %a) 725 ret <4 x float> %v 726} 727 728; CHECK-LABEL: floor_v4f32: 729; SIMD128-NEXT: .functype floor_v4f32 (v128) -> (v128){{$}} 730; SIMD128-NEXT: f32x4.floor $push[[R:[0-9]+]]=, $0{{$}} 731; SIMD128-NEXT: return $pop[[R]]{{$}} 732declare <4 x float> @llvm.wasm.floor.v4f32(<4 x float>) 733define <4 x float> @floor_v4f32(<4 x float> %a) { 734 %v = call <4 x float> @llvm.wasm.floor.v4f32(<4 x float> %a) 735 ret <4 x float> %v 736} 737 738; CHECK-LABEL: trunc_v4f32: 739; SIMD128-NEXT: .functype trunc_v4f32 (v128) -> (v128){{$}} 740; SIMD128-NEXT: f32x4.trunc $push[[R:[0-9]+]]=, $0{{$}} 741; SIMD128-NEXT: return $pop[[R]]{{$}} 742declare <4 x float> @llvm.wasm.trunc.v4f32(<4 x float>) 743define <4 x float> @trunc_v4f32(<4 x float> %a) { 744 %v = call <4 x float> @llvm.wasm.trunc.v4f32(<4 x float> %a) 745 ret <4 x float> %v 746} 747 748; CHECK-LABEL: nearest_v4f32: 749; SIMD128-NEXT: .functype nearest_v4f32 (v128) -> (v128){{$}} 750; SIMD128-NEXT: f32x4.nearest $push[[R:[0-9]+]]=, $0{{$}} 751; SIMD128-NEXT: return $pop[[R]]{{$}} 752declare <4 x float> @llvm.wasm.nearest.v4f32(<4 x float>) 753define <4 x float> @nearest_v4f32(<4 x float> %a) { 754 %v = call <4 x float> @llvm.wasm.nearest.v4f32(<4 x float> %a) 755 ret <4 x float> %v 756} 757 758; CHECK-LABEL: qfma_v4f32: 759; SIMD128-NEXT: .functype qfma_v4f32 (v128, v128, v128) -> (v128){{$}} 760; SIMD128-NEXT: f32x4.qfma $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 761; SIMD128-NEXT: return $pop[[R]]{{$}} 762declare <4 x float> @llvm.wasm.qfma.v4f32(<4 x float>, <4 x float>, <4 x float>) 763define <4 x float> @qfma_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { 764 %v = call <4 x float> @llvm.wasm.qfma.v4f32( 765 <4 x float> %a, <4 x float> %b, <4 x float> %c 766 ) 767 ret <4 x float> %v 768} 769 770; CHECK-LABEL: qfms_v4f32: 771; SIMD128-NEXT: .functype qfms_v4f32 (v128, v128, v128) -> (v128){{$}} 772; SIMD128-NEXT: f32x4.qfms $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 773; SIMD128-NEXT: return $pop[[R]]{{$}} 774declare <4 x float> @llvm.wasm.qfms.v4f32(<4 x float>, <4 x float>, <4 x float>) 775define <4 x float> @qfms_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { 776 %v = call <4 x float> @llvm.wasm.qfms.v4f32( 777 <4 x float> %a, <4 x float> %b, <4 x float> %c 778 ) 779 ret <4 x float> %v 780} 781 782; ============================================================================== 783; 2 x f64 784; ============================================================================== 785; CHECK-LABEL: bitselect_v2f64: 786; SIMD128-NEXT: .functype bitselect_v2f64 (v128, v128, v128) -> (v128){{$}} 787; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 788; SIMD128-NEXT: return $pop[[R]]{{$}} 789declare <2 x double> @llvm.wasm.bitselect.v2f64(<2 x double>, <2 x double>, <2 x double>) 790define <2 x double> @bitselect_v2f64(<2 x double> %v1, <2 x double> %v2, <2 x double> %c) { 791 %a = call <2 x double> @llvm.wasm.bitselect.v2f64( 792 <2 x double> %v1, <2 x double> %v2, <2 x double> %c 793 ) 794 ret <2 x double> %a 795} 796 797; CHECK-LABEL: pmin_v2f64: 798; SIMD128-NEXT: .functype pmin_v2f64 (v128, v128) -> (v128){{$}} 799; SIMD128-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 800; SIMD128-NEXT: return $pop[[R]]{{$}} 801declare <2 x double> @llvm.wasm.pmin.v2f64(<2 x double>, <2 x double>) 802define <2 x double> @pmin_v2f64(<2 x double> %a, <2 x double> %b) { 803 %v = call <2 x double> @llvm.wasm.pmin.v2f64(<2 x double> %a, <2 x double> %b) 804 ret <2 x double> %v 805} 806 807; CHECK-LABEL: pmax_v2f64: 808; SIMD128-NEXT: .functype pmax_v2f64 (v128, v128) -> (v128){{$}} 809; SIMD128-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 810; SIMD128-NEXT: return $pop[[R]]{{$}} 811declare <2 x double> @llvm.wasm.pmax.v2f64(<2 x double>, <2 x double>) 812define <2 x double> @pmax_v2f64(<2 x double> %a, <2 x double> %b) { 813 %v = call <2 x double> @llvm.wasm.pmax.v2f64(<2 x double> %a, <2 x double> %b) 814 ret <2 x double> %v 815} 816 817; CHECK-LABEL: ceil_v2f64: 818; SIMD128-NEXT: .functype ceil_v2f64 (v128) -> (v128){{$}} 819; SIMD128-NEXT: f64x2.ceil $push[[R:[0-9]+]]=, $0{{$}} 820; SIMD128-NEXT: return $pop[[R]]{{$}} 821declare <2 x double> @llvm.wasm.ceil.v2f64(<2 x double>) 822define <2 x double> @ceil_v2f64(<2 x double> %a) { 823 %v = call <2 x double> @llvm.wasm.ceil.v2f64(<2 x double> %a) 824 ret <2 x double> %v 825} 826 827; CHECK-LABEL: floor_v2f64: 828; SIMD128-NEXT: .functype floor_v2f64 (v128) -> (v128){{$}} 829; SIMD128-NEXT: f64x2.floor $push[[R:[0-9]+]]=, $0{{$}} 830; SIMD128-NEXT: return $pop[[R]]{{$}} 831declare <2 x double> @llvm.wasm.floor.v2f64(<2 x double>) 832define <2 x double> @floor_v2f64(<2 x double> %a) { 833 %v = call <2 x double> @llvm.wasm.floor.v2f64(<2 x double> %a) 834 ret <2 x double> %v 835} 836 837; CHECK-LABEL: trunc_v2f64: 838; SIMD128-NEXT: .functype trunc_v2f64 (v128) -> (v128){{$}} 839; SIMD128-NEXT: f64x2.trunc $push[[R:[0-9]+]]=, $0{{$}} 840; SIMD128-NEXT: return $pop[[R]]{{$}} 841declare <2 x double> @llvm.wasm.trunc.v2f64(<2 x double>) 842define <2 x double> @trunc_v2f64(<2 x double> %a) { 843 %v = call <2 x double> @llvm.wasm.trunc.v2f64(<2 x double> %a) 844 ret <2 x double> %v 845} 846 847; CHECK-LABEL: nearest_v2f64: 848; SIMD128-NEXT: .functype nearest_v2f64 (v128) -> (v128){{$}} 849; SIMD128-NEXT: f64x2.nearest $push[[R:[0-9]+]]=, $0{{$}} 850; SIMD128-NEXT: return $pop[[R]]{{$}} 851declare <2 x double> @llvm.wasm.nearest.v2f64(<2 x double>) 852define <2 x double> @nearest_v2f64(<2 x double> %a) { 853 %v = call <2 x double> @llvm.wasm.nearest.v2f64(<2 x double> %a) 854 ret <2 x double> %v 855} 856 857; CHECK-LABEL: qfma_v2f64: 858; SIMD128-NEXT: .functype qfma_v2f64 (v128, v128, v128) -> (v128){{$}} 859; SIMD128-NEXT: f64x2.qfma $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 860; SIMD128-NEXT: return $pop[[R]]{{$}} 861declare <2 x double> @llvm.wasm.qfma.v2f64(<2 x double>, <2 x double>, <2 x double>) 862define <2 x double> @qfma_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { 863 %v = call <2 x double> @llvm.wasm.qfma.v2f64( 864 <2 x double> %a, <2 x double> %b, <2 x double> %c 865 ) 866 ret <2 x double> %v 867} 868 869; CHECK-LABEL: qfms_v2f64: 870; SIMD128-NEXT: .functype qfms_v2f64 (v128, v128, v128) -> (v128){{$}} 871; SIMD128-NEXT: f64x2.qfms $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 872; SIMD128-NEXT: return $pop[[R]]{{$}} 873declare <2 x double> @llvm.wasm.qfms.v2f64(<2 x double>, <2 x double>, <2 x double>) 874define <2 x double> @qfms_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { 875 %v = call <2 x double> @llvm.wasm.qfms.v2f64( 876 <2 x double> %a, <2 x double> %b, <2 x double> %c 877 ) 878 ret <2 x double> %v 879} 880