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1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
2; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
3
4; Test that vector sign extensions lower to shifts
5
6target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
7target triple = "wasm32-unknown-unknown"
8
9; CHECK-LABEL: sext_v16i8:
10; NO-SIMD128-NOT: i8x16
11; SIMD128-NEXT: .functype sext_v16i8 (v128) -> (v128){{$}}
12; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 7{{$}}
13; SIMD128-NEXT: i8x16.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
14; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 7{{$}}
15; SIMD128-NEXT: i8x16.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
16; SIMD128-NEXT: return $pop[[R]]{{$}}
17define <16 x i8> @sext_v16i8(<16 x i1> %x) {
18  %res = sext <16 x i1> %x to <16 x i8>
19  ret <16 x i8> %res
20}
21
22; CHECK-LABEL: sext_v8i16:
23; NO-SIMD128-NOT: i16x8
24; SIMD128-NEXT: .functype sext_v8i16 (v128) -> (v128){{$}}
25; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 15{{$}}
26; SIMD128-NEXT: i16x8.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
27; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 15{{$}}
28; SIMD128-NEXT: i16x8.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
29; SIMD128-NEXT: return $pop[[R]]{{$}}
30define <8 x i16> @sext_v8i16(<8 x i1> %x) {
31  %res = sext <8 x i1> %x to <8 x i16>
32  ret <8 x i16> %res
33}
34
35; CHECK-LABEL: sext_v4i32:
36; NO-SIMD128-NOT: i32x4
37; SIMD128-NEXT: .functype sext_v4i32 (v128) -> (v128){{$}}
38; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 31{{$}}
39; SIMD128-NEXT: i32x4.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
40; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 31{{$}}
41; SIMD128-NEXT: i32x4.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
42; SIMD128-NEXT: return $pop[[R]]{{$}}
43define <4 x i32> @sext_v4i32(<4 x i1> %x) {
44  %res = sext <4 x i1> %x to <4 x i32>
45  ret <4 x i32> %res
46}
47
48; CHECK-LABEL: sext_v2i64:
49; NO-SIMD128-NOT: i64x2
50; SIMD128-NEXT: .functype sext_v2i64 (v128) -> (v128){{$}}
51; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 63{{$}}
52; SIMD128-NEXT: i64x2.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
53; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 63{{$}}
54; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
55; SIMD128-NEXT: return $pop[[R]]{{$}}
56define <2 x i64> @sext_v2i64(<2 x i1> %x) {
57  %res = sext <2 x i1> %x to <2 x i64>
58  ret <2 x i64> %res
59}
60
61; CHECK-LABEL: sext_inreg_i8_to_i16:
62; SIMD128-NEXT: .functype sext_inreg_i8_to_i16 (v128) -> (i32){{$}}
63; SIMD128-NEXT: i8x16.extract_lane_s $push[[R:[0-9]+]]=, $0, 2{{$}}
64; SIMD128-NEXT: return $pop[[R]]{{$}}
65define i16 @sext_inreg_i8_to_i16(<8 x i16> %x) {
66  %lane = extractelement <8 x i16> %x, i32 1
67  %a = shl i16 %lane, 8
68  %res = ashr i16 %a, 8
69  ret i16 %res
70}
71
72; CHECK-LABEL: sext_inreg_i8_to_i32:
73; SIMD128-NEXT: .functype sext_inreg_i8_to_i32 (v128) -> (i32){{$}}
74; SIMD128-NEXT: i8x16.extract_lane_s $push[[R:[0-9]+]]=, $0, 4{{$}}
75; SIMD128-NEXT: return $pop[[R]]{{$}}
76define i32 @sext_inreg_i8_to_i32(<4 x i32> %x) {
77  %lane = extractelement <4 x i32> %x, i32 1
78  %a = shl i32 %lane, 24
79  %res = ashr i32 %a, 24
80  ret i32 %res
81}
82
83; CHECK-LABEL: sext_inreg_i16_to_i32:
84; SIMD128-NEXT: .functype sext_inreg_i16_to_i32 (v128) -> (i32){{$}}
85; SIMD128-NEXT: i16x8.extract_lane_s $push[[R:[0-9]+]]=, $0, 2{{$}}
86; SIMD128-NEXT: return $pop[[R]]{{$}}
87define i32 @sext_inreg_i16_to_i32(<4 x i32> %x) {
88  %lane = extractelement <4 x i32> %x, i32 1
89  %a = shl i32 %lane, 16
90  %res = ashr i32 %a, 16
91  ret i32 %res
92}
93
94; CHECK-LABEL: sext_inreg_i8_to_i64:
95; SIMD128-NEXT: .functype sext_inreg_i8_to_i64 (v128) -> (i64){{$}}
96; SIMD128-NEXT: i64x2.extract_lane $push[[T0:[0-9]+]]=, $0, 1{{$}}
97; SIMD128-NEXT: i64.const $push[[T1:[0-9]+]]=, 56{{$}}
98; SIMD128-NEXT: i64.shl $push[[T2:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
99; SIMD128-NEXT: i64.const $push[[T3:[0-9]+]]=, 56{{$}}
100; SIMD128-NEXT: i64.shr_s $push[[R:[0-9]+]]=, $pop[[T2]], $pop[[T3]]{{$}}
101; SIMD128-NEXT: return $pop[[R]]{{$}}
102define i64 @sext_inreg_i8_to_i64(<2 x i64> %x) {
103  %lane = extractelement <2 x i64> %x, i32 1
104  %a = shl i64 %lane, 56
105  %res = ashr i64 %a, 56
106  ret i64 %res
107}
108
109; CHECK-LABEL: sext_inreg_i16_to_i64:
110; SIMD128-NEXT: .functype sext_inreg_i16_to_i64 (v128) -> (i64){{$}}
111; SIMD128-NEXT: i64x2.extract_lane $push[[T0:[0-9]+]]=, $0, 1{{$}}
112; SIMD128-NEXT: i64.const $push[[T1:[0-9]+]]=, 48{{$}}
113; SIMD128-NEXT: i64.shl $push[[T2:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
114; SIMD128-NEXT: i64.const $push[[T3:[0-9]+]]=, 48{{$}}
115; SIMD128-NEXT: i64.shr_s $push[[R:[0-9]+]]=, $pop[[T2]], $pop[[T3]]{{$}}
116; SIMD128-NEXT: return $pop[[R]]{{$}}
117define i64 @sext_inreg_i16_to_i64(<2 x i64> %x) {
118  %lane = extractelement <2 x i64> %x, i32 1
119  %a = shl i64 %lane, 48
120  %res = ashr i64 %a, 48
121  ret i64 %res
122}
123
124; CHECK-LABEL: sext_inreg_i32_to_i64:
125; NO-SIMD128-NOT: i64x2
126; SIMD128-NEXT: .functype sext_inreg_i32_to_i64 (v128) -> (i64){{$}}
127; SIMD128-NEXT: i64x2.extract_lane $push[[T0:[0-9]+]]=, $0, 1{{$}}
128; SIMD128-NEXT: i64.const $push[[T1:[0-9]+]]=, 32{{$}}
129; SIMD128-NEXT: i64.shl $push[[T2:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
130; SIMD128-NEXT: i64.const $push[[T3:[0-9]+]]=, 32{{$}}
131; SIMD128-NEXT: i64.shr_s $push[[R:[0-9]+]]=, $pop[[T2]], $pop[[T3]]{{$}}
132; SIMD128-NEXT: return $pop[[R]]{{$}}
133define i64 @sext_inreg_i32_to_i64(<2 x i64> %x) {
134  %lane = extractelement <2 x i64> %x, i32 1
135  %a = shl i64 %lane, 32
136  %res = ashr i64 %a, 32
137  ret i64 %res
138}
139