1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL 3 4--- | 5 define i64 @test_zext_i1(i8 %a) { 6 %val = trunc i8 %a to i1 7 %r = zext i1 %val to i64 8 ret i64 %r 9 } 10 11 define i64 @test_sext_i8(i8 %val) { 12 %r = sext i8 %val to i64 13 ret i64 %r 14 } 15 16 define i64 @test_sext_i16(i16 %val) { 17 %r = sext i16 %val to i64 18 ret i64 %r 19 } 20 21 define void @anyext_s64_from_s1() { ret void } 22 define void @anyext_s64_from_s8() { ret void } 23 define void @anyext_s64_from_s16() { ret void } 24 define void @anyext_s64_from_s32() { ret void } 25... 26--- 27name: test_zext_i1 28alignment: 16 29legalized: true 30regBankSelected: true 31registers: 32 - { id: 0, class: gpr } 33 - { id: 1, class: gpr } 34 - { id: 2, class: gpr } 35body: | 36 bb.1 (%ir-block.0): 37 liveins: $edi 38 39 ; ALL-LABEL: name: test_zext_i1 40 ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY $dil 41 ; ALL: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF 42 ; ALL: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_8bit 43 ; ALL: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags 44 ; ALL: $rax = COPY [[AND64ri8_]] 45 ; ALL: RET 0, implicit $rax 46 %0(s8) = COPY $dil 47 %1(s1) = G_TRUNC %0(s8) 48 %2(s64) = G_ZEXT %1(s1) 49 $rax = COPY %2(s64) 50 RET 0, implicit $rax 51 52... 53--- 54name: test_sext_i8 55alignment: 16 56legalized: true 57regBankSelected: true 58registers: 59 - { id: 0, class: gpr } 60 - { id: 1, class: gpr } 61body: | 62 bb.1 (%ir-block.0): 63 liveins: $edi 64 65 ; ALL-LABEL: name: test_sext_i8 66 ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY $dil 67 ; ALL: [[MOVSX64rr8_:%[0-9]+]]:gr64 = MOVSX64rr8 [[COPY]] 68 ; ALL: $rax = COPY [[MOVSX64rr8_]] 69 ; ALL: RET 0, implicit $rax 70 %0(s8) = COPY $dil 71 %1(s64) = G_SEXT %0(s8) 72 $rax = COPY %1(s64) 73 RET 0, implicit $rax 74 75... 76--- 77name: test_sext_i16 78alignment: 16 79legalized: true 80regBankSelected: true 81registers: 82 - { id: 0, class: gpr } 83 - { id: 1, class: gpr } 84body: | 85 bb.1 (%ir-block.0): 86 liveins: $edi 87 88 ; ALL-LABEL: name: test_sext_i16 89 ; ALL: [[COPY:%[0-9]+]]:gr16 = COPY $di 90 ; ALL: [[MOVSX64rr16_:%[0-9]+]]:gr64 = MOVSX64rr16 [[COPY]] 91 ; ALL: $rax = COPY [[MOVSX64rr16_]] 92 ; ALL: RET 0, implicit $rax 93 %0(s16) = COPY $di 94 %1(s64) = G_SEXT %0(s16) 95 $rax = COPY %1(s64) 96 RET 0, implicit $rax 97 98... 99--- 100name: anyext_s64_from_s1 101alignment: 16 102legalized: true 103regBankSelected: true 104registers: 105 - { id: 0, class: gpr } 106 - { id: 1, class: gpr } 107 - { id: 2, class: gpr } 108body: | 109 bb.1 (%ir-block.0): 110 liveins: $edi 111 112 ; ALL-LABEL: name: anyext_s64_from_s1 113 ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi 114 ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit 115 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit 116 ; ALL: $rax = COPY [[SUBREG_TO_REG]] 117 ; ALL: RET 0, implicit $rax 118 %0(s64) = COPY $rdi 119 %1(s1) = G_TRUNC %0(s64) 120 %2(s64) = G_ANYEXT %1(s1) 121 $rax = COPY %2(s64) 122 RET 0, implicit $rax 123... 124--- 125name: anyext_s64_from_s8 126alignment: 16 127legalized: true 128regBankSelected: true 129registers: 130 - { id: 0, class: gpr } 131 - { id: 1, class: gpr } 132 - { id: 2, class: gpr } 133body: | 134 bb.1 (%ir-block.0): 135 liveins: $edi 136 137 ; ALL-LABEL: name: anyext_s64_from_s8 138 ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi 139 ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit 140 ; ALL: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]] 141 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOVZX32rr8_]], %subreg.sub_32bit 142 ; ALL: $rax = COPY [[SUBREG_TO_REG]] 143 ; ALL: RET 0, implicit $rax 144 %0(s64) = COPY $rdi 145 %1(s8) = G_TRUNC %0(s64) 146 %2(s64) = G_ANYEXT %1(s8) 147 $rax = COPY %2(s64) 148 RET 0, implicit $rax 149... 150--- 151name: anyext_s64_from_s16 152alignment: 16 153legalized: true 154regBankSelected: true 155registers: 156 - { id: 0, class: gpr } 157 - { id: 1, class: gpr } 158 - { id: 2, class: gpr } 159body: | 160 bb.1 (%ir-block.0): 161 liveins: $edi 162 163 ; ALL-LABEL: name: anyext_s64_from_s16 164 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 165 ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit 166 ; ALL: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]] 167 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOVZX32rr16_]], %subreg.sub_32bit 168 ; ALL: $rax = COPY [[SUBREG_TO_REG]] 169 ; ALL: RET 0, implicit $rax 170 %0(s64) = COPY $rdi 171 %1(s16) = G_TRUNC %0(s64) 172 %2(s64) = G_ANYEXT %1(s16) 173 $rax = COPY %2(s64) 174 RET 0, implicit $rax 175... 176--- 177name: anyext_s64_from_s32 178alignment: 16 179legalized: true 180regBankSelected: true 181registers: 182 - { id: 0, class: gpr } 183 - { id: 1, class: gpr } 184 - { id: 2, class: gpr } 185body: | 186 bb.1 (%ir-block.0): 187 liveins: $edi 188 189 ; ALL-LABEL: name: anyext_s64_from_s32 190 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 191 ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit 192 ; ALL: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF 193 ; ALL: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_32bit 194 ; ALL: $rax = COPY [[INSERT_SUBREG]] 195 ; ALL: RET 0, implicit $rax 196 %0(s64) = COPY $rdi 197 %1(s32) = G_TRUNC %0(s64) 198 %2(s64) = G_ANYEXT %1(s32) 199 $rax = COPY %2(s64) 200 RET 0, implicit $rax 201... 202