1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512F 3--- | 4 define <16 x i32> @test_load_v16i32_noalign(<16 x i32>* %p1) { 5 %r = load <16 x i32>, <16 x i32>* %p1, align 1 6 ret <16 x i32> %r 7 } 8 9 define <16 x i32> @test_load_v16i32_align(<16 x i32>* %p1) { 10 %r = load <16 x i32>, <16 x i32>* %p1, align 32 11 ret <16 x i32> %r 12 } 13 14 define void @test_store_v16i32_noalign(<16 x i32> %val, <16 x i32>* %p1) { 15 store <16 x i32> %val, <16 x i32>* %p1, align 1 16 ret void 17 } 18 19 define void @test_store_v16i32_align(<16 x i32> %val, <16 x i32>* %p1) { 20 store <16 x i32> %val, <16 x i32>* %p1, align 32 21 ret void 22 } 23 24... 25--- 26name: test_load_v16i32_noalign 27alignment: 16 28legalized: true 29regBankSelected: true 30registers: 31 - { id: 0, class: gpr } 32 - { id: 1, class: vecr } 33body: | 34 bb.1 (%ir-block.0): 35 liveins: $rdi 36 37 ; AVX512F-LABEL: name: test_load_v16i32_noalign 38 ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 39 ; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, $noreg, 0, $noreg :: (load 64 from %ir.p1, align 1) 40 ; AVX512F: $zmm0 = COPY [[VMOVUPSZrm]] 41 ; AVX512F: RET 0, implicit $zmm0 42 %0(p0) = COPY $rdi 43 %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 1) 44 $zmm0 = COPY %1(<16 x s32>) 45 RET 0, implicit $zmm0 46 47... 48--- 49name: test_load_v16i32_align 50alignment: 16 51legalized: true 52regBankSelected: true 53registers: 54 - { id: 0, class: gpr } 55 - { id: 1, class: vecr } 56body: | 57 bb.1 (%ir-block.0): 58 liveins: $rdi 59 60 ; AVX512F-LABEL: name: test_load_v16i32_align 61 ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 62 ; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, $noreg, 0, $noreg :: (load 64 from %ir.p1, align 32) 63 ; AVX512F: $zmm0 = COPY [[VMOVUPSZrm]] 64 ; AVX512F: RET 0, implicit $zmm0 65 %0(p0) = COPY $rdi 66 %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 32) 67 $zmm0 = COPY %1(<16 x s32>) 68 RET 0, implicit $zmm0 69 70... 71--- 72name: test_store_v16i32_noalign 73alignment: 16 74legalized: true 75regBankSelected: true 76registers: 77 - { id: 0, class: vecr } 78 - { id: 1, class: gpr } 79body: | 80 bb.1 (%ir-block.0): 81 liveins: $rdi, $zmm0 82 83 ; AVX512F-LABEL: name: test_store_v16i32_noalign 84 ; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0 85 ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi 86 ; AVX512F: VMOVUPSZmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store 64 into %ir.p1, align 1) 87 ; AVX512F: RET 0 88 %0(<16 x s32>) = COPY $zmm0 89 %1(p0) = COPY $rdi 90 G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 1) 91 RET 0 92 93... 94--- 95name: test_store_v16i32_align 96alignment: 16 97legalized: true 98regBankSelected: true 99registers: 100 - { id: 0, class: vecr } 101 - { id: 1, class: gpr } 102body: | 103 bb.1 (%ir-block.0): 104 liveins: $rdi, $zmm0 105 106 ; AVX512F-LABEL: name: test_store_v16i32_align 107 ; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0 108 ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi 109 ; AVX512F: VMOVUPSZmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store 64 into %ir.p1, align 32) 110 ; AVX512F: RET 0 111 %0(<16 x s32>) = COPY $zmm0 112 %1(p0) = COPY $rdi 113 G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 32) 114 RET 0 115 116... 117