1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL 3 4--- | 5 6 define i8 @test_i8(i32 %a, i8 %f, i8 %t) { 7 entry: 8 %cmp = icmp sgt i32 %a, 0 9 br i1 %cmp, label %cond.true, label %cond.false 10 11 cond.true: ; preds = %entry 12 br label %cond.end 13 14 cond.false: ; preds = %entry 15 br label %cond.end 16 17 cond.end: ; preds = %cond.false, %cond.true 18 %cond = phi i8 [ %f, %cond.true ], [ %t, %cond.false ] 19 ret i8 %cond 20 } 21 22 define i16 @test_i16(i32 %a, i16 %f, i16 %t) { 23 entry: 24 %cmp = icmp sgt i32 %a, 0 25 br i1 %cmp, label %cond.true, label %cond.false 26 27 cond.true: ; preds = %entry 28 br label %cond.end 29 30 cond.false: ; preds = %entry 31 br label %cond.end 32 33 cond.end: ; preds = %cond.false, %cond.true 34 %cond = phi i16 [ %f, %cond.true ], [ %t, %cond.false ] 35 ret i16 %cond 36 } 37 38 define i32 @test_i32(i32 %a, i32 %f, i32 %t) { 39 entry: 40 %cmp = icmp sgt i32 %a, 0 41 br i1 %cmp, label %cond.true, label %cond.false 42 43 cond.true: ; preds = %entry 44 br label %cond.end 45 46 cond.false: ; preds = %entry 47 br label %cond.end 48 49 cond.end: ; preds = %cond.false, %cond.true 50 %cond = phi i32 [ %f, %cond.true ], [ %t, %cond.false ] 51 ret i32 %cond 52 } 53 54 define i64 @test_i64(i32 %a, i64 %f, i64 %t) { 55 entry: 56 %cmp = icmp sgt i32 %a, 0 57 br i1 %cmp, label %cond.true, label %cond.false 58 59 cond.true: ; preds = %entry 60 br label %cond.end 61 62 cond.false: ; preds = %entry 63 br label %cond.end 64 65 cond.end: ; preds = %cond.false, %cond.true 66 %cond = phi i64 [ %f, %cond.true ], [ %t, %cond.false ] 67 ret i64 %cond 68 } 69 70 define float @test_float(i32 %a, float %f, float %t) { 71 entry: 72 %cmp = icmp sgt i32 %a, 0 73 br i1 %cmp, label %cond.true, label %cond.false 74 75 cond.true: ; preds = %entry 76 br label %cond.end 77 78 cond.false: ; preds = %entry 79 br label %cond.end 80 81 cond.end: ; preds = %cond.false, %cond.true 82 %cond = phi float [ %f, %cond.true ], [ %t, %cond.false ] 83 ret float %cond 84 } 85 86 define double @test_double(i32 %a, double %f, double %t) { 87 entry: 88 %cmp = icmp sgt i32 %a, 0 89 br i1 %cmp, label %cond.true, label %cond.false 90 91 cond.true: ; preds = %entry 92 br label %cond.end 93 94 cond.false: ; preds = %entry 95 br label %cond.end 96 97 cond.end: ; preds = %cond.false, %cond.true 98 %cond = phi double [ %f, %cond.true ], [ %t, %cond.false ] 99 ret double %cond 100 } 101 102... 103--- 104name: test_i8 105alignment: 16 106legalized: true 107regBankSelected: true 108tracksRegLiveness: true 109registers: 110 - { id: 0, class: gpr, preferred-register: '' } 111 - { id: 1, class: gpr, preferred-register: '' } 112 - { id: 2, class: gpr, preferred-register: '' } 113 - { id: 3, class: gpr, preferred-register: '' } 114 - { id: 4, class: gpr, preferred-register: '' } 115 - { id: 5, class: gpr, preferred-register: '' } 116 - { id: 6, class: gpr, preferred-register: '' } 117 - { id: 7, class: gpr, preferred-register: '' } 118body: | 119 ; ALL-LABEL: name: test_i8 120 ; ALL: bb.0.entry: 121 ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000) 122 ; ALL: liveins: $edi, $edx, $esi 123 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi 124 ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 125 ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit 126 ; ALL: [[COPY3:%[0-9]+]]:gr32 = COPY $edx 127 ; ALL: [[COPY4:%[0-9]+]]:gr8 = COPY [[COPY3]].sub_8bit 128 ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags 129 ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags 130 ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags 131 ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags 132 ; ALL: JCC_1 %bb.2, 5, implicit $eflags 133 ; ALL: bb.1.cond.false: 134 ; ALL: successors: %bb.2(0x80000000) 135 ; ALL: bb.2.cond.end: 136 ; ALL: [[PHI:%[0-9]+]]:gr8 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0 137 ; ALL: $al = COPY [[PHI]] 138 ; ALL: RET 0, implicit $al 139 bb.1.entry: 140 successors: %bb.3(0x40000000), %bb.2(0x40000000) 141 liveins: $edi, $edx, $esi 142 143 %0:gpr(s32) = COPY $edi 144 %3:gpr(s32) = COPY $esi 145 %1:gpr(s8) = G_TRUNC %3(s32) 146 %4:gpr(s32) = COPY $edx 147 %2:gpr(s8) = G_TRUNC %4(s32) 148 %5:gpr(s32) = G_CONSTANT i32 0 149 %8:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5 150 %6:gpr(s1) = G_TRUNC %8(s8) 151 G_BRCOND %6(s1), %bb.3 152 153 bb.2.cond.false: 154 successors: %bb.3(0x80000000) 155 156 157 bb.3.cond.end: 158 %7:gpr(s8) = G_PHI %2(s8), %bb.2, %1(s8), %bb.1 159 $al = COPY %7(s8) 160 RET 0, implicit $al 161 162... 163--- 164name: test_i16 165alignment: 16 166legalized: true 167regBankSelected: true 168tracksRegLiveness: true 169registers: 170 - { id: 0, class: gpr, preferred-register: '' } 171 - { id: 1, class: gpr, preferred-register: '' } 172 - { id: 2, class: gpr, preferred-register: '' } 173 - { id: 3, class: gpr, preferred-register: '' } 174 - { id: 4, class: gpr, preferred-register: '' } 175 - { id: 5, class: gpr, preferred-register: '' } 176 - { id: 6, class: gpr, preferred-register: '' } 177 - { id: 7, class: gpr, preferred-register: '' } 178body: | 179 ; ALL-LABEL: name: test_i16 180 ; ALL: bb.0.entry: 181 ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000) 182 ; ALL: liveins: $edi, $edx, $esi 183 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi 184 ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 185 ; ALL: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit 186 ; ALL: [[COPY3:%[0-9]+]]:gr32 = COPY $edx 187 ; ALL: [[COPY4:%[0-9]+]]:gr16 = COPY [[COPY3]].sub_16bit 188 ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags 189 ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags 190 ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags 191 ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags 192 ; ALL: JCC_1 %bb.2, 5, implicit $eflags 193 ; ALL: bb.1.cond.false: 194 ; ALL: successors: %bb.2(0x80000000) 195 ; ALL: bb.2.cond.end: 196 ; ALL: [[PHI:%[0-9]+]]:gr16 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0 197 ; ALL: $ax = COPY [[PHI]] 198 ; ALL: RET 0, implicit $ax 199 bb.1.entry: 200 successors: %bb.3(0x40000000), %bb.2(0x40000000) 201 liveins: $edi, $edx, $esi 202 203 %0:gpr(s32) = COPY $edi 204 %3:gpr(s32) = COPY $esi 205 %1:gpr(s16) = G_TRUNC %3(s32) 206 %4:gpr(s32) = COPY $edx 207 %2:gpr(s16) = G_TRUNC %4(s32) 208 %5:gpr(s32) = G_CONSTANT i32 0 209 %8:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5 210 %6:gpr(s1) = G_TRUNC %8(s8) 211 G_BRCOND %6(s1), %bb.3 212 213 bb.2.cond.false: 214 successors: %bb.3(0x80000000) 215 216 217 bb.3.cond.end: 218 %7:gpr(s16) = G_PHI %2(s16), %bb.2, %1(s16), %bb.1 219 $ax = COPY %7(s16) 220 RET 0, implicit $ax 221 222... 223--- 224name: test_i32 225alignment: 16 226legalized: true 227regBankSelected: true 228tracksRegLiveness: true 229registers: 230 - { id: 0, class: gpr, preferred-register: '' } 231 - { id: 1, class: gpr, preferred-register: '' } 232 - { id: 2, class: gpr, preferred-register: '' } 233 - { id: 3, class: gpr, preferred-register: '' } 234 - { id: 4, class: gpr, preferred-register: '' } 235 - { id: 5, class: gpr, preferred-register: '' } 236 - { id: 6, class: gpr, preferred-register: '' } 237body: | 238 ; ALL-LABEL: name: test_i32 239 ; ALL: bb.0.entry: 240 ; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000) 241 ; ALL: liveins: $edi, $edx, $esi 242 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi 243 ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 244 ; ALL: [[COPY2:%[0-9]+]]:gr32 = COPY $edx 245 ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags 246 ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags 247 ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags 248 ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags 249 ; ALL: JCC_1 %bb.1, 5, implicit $eflags 250 ; ALL: JMP_1 %bb.2 251 ; ALL: bb.1.cond.true: 252 ; ALL: successors: %bb.3(0x80000000) 253 ; ALL: JMP_1 %bb.3 254 ; ALL: bb.2.cond.false: 255 ; ALL: successors: %bb.3(0x80000000) 256 ; ALL: bb.3.cond.end: 257 ; ALL: [[PHI:%[0-9]+]]:gr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2 258 ; ALL: $eax = COPY [[PHI]] 259 ; ALL: RET 0, implicit $eax 260 bb.1.entry: 261 successors: %bb.2(0x40000000), %bb.3(0x40000000) 262 liveins: $edi, $edx, $esi 263 264 %0(s32) = COPY $edi 265 %1(s32) = COPY $esi 266 %2(s32) = COPY $edx 267 %3(s32) = G_CONSTANT i32 0 268 %6(s8) = G_ICMP intpred(sgt), %0(s32), %3 269 %4:gpr(s1) = G_TRUNC %6(s8) 270 G_BRCOND %4(s1), %bb.2 271 G_BR %bb.3 272 273 bb.2.cond.true: 274 successors: %bb.4(0x80000000) 275 276 G_BR %bb.4 277 278 bb.3.cond.false: 279 successors: %bb.4(0x80000000) 280 281 282 bb.4.cond.end: 283 %5(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3 284 $eax = COPY %5(s32) 285 RET 0, implicit $eax 286 287... 288--- 289name: test_i64 290alignment: 16 291legalized: true 292regBankSelected: true 293tracksRegLiveness: true 294registers: 295 - { id: 0, class: gpr, preferred-register: '' } 296 - { id: 1, class: gpr, preferred-register: '' } 297 - { id: 2, class: gpr, preferred-register: '' } 298 - { id: 3, class: gpr, preferred-register: '' } 299 - { id: 4, class: gpr, preferred-register: '' } 300 - { id: 5, class: gpr, preferred-register: '' } 301 - { id: 6, class: gpr, preferred-register: '' } 302body: | 303 ; ALL-LABEL: name: test_i64 304 ; ALL: bb.0.entry: 305 ; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000) 306 ; ALL: liveins: $edi, $rdx, $rsi 307 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi 308 ; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi 309 ; ALL: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx 310 ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags 311 ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags 312 ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags 313 ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags 314 ; ALL: JCC_1 %bb.1, 5, implicit $eflags 315 ; ALL: JMP_1 %bb.2 316 ; ALL: bb.1.cond.true: 317 ; ALL: successors: %bb.3(0x80000000) 318 ; ALL: JMP_1 %bb.3 319 ; ALL: bb.2.cond.false: 320 ; ALL: successors: %bb.3(0x80000000) 321 ; ALL: bb.3.cond.end: 322 ; ALL: [[PHI:%[0-9]+]]:gr64 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2 323 ; ALL: $rax = COPY [[PHI]] 324 ; ALL: RET 0, implicit $rax 325 bb.1.entry: 326 successors: %bb.2(0x40000000), %bb.3(0x40000000) 327 liveins: $edi, $rdx, $rsi 328 329 %0(s32) = COPY $edi 330 %1(s64) = COPY $rsi 331 %2(s64) = COPY $rdx 332 %3(s32) = G_CONSTANT i32 0 333 %6(s8) = G_ICMP intpred(sgt), %0(s32), %3 334 %4:gpr(s1) = G_TRUNC %6(s8) 335 G_BRCOND %4(s1), %bb.2 336 G_BR %bb.3 337 338 bb.2.cond.true: 339 successors: %bb.4(0x80000000) 340 341 G_BR %bb.4 342 343 bb.3.cond.false: 344 successors: %bb.4(0x80000000) 345 346 347 bb.4.cond.end: 348 %5(s64) = G_PHI %1(s64), %bb.2, %2(s64), %bb.3 349 $rax = COPY %5(s64) 350 RET 0, implicit $rax 351 352... 353--- 354name: test_float 355alignment: 16 356legalized: true 357regBankSelected: true 358tracksRegLiveness: true 359registers: 360 - { id: 0, class: gpr, preferred-register: '' } 361 - { id: 1, class: vecr, preferred-register: '' } 362 - { id: 2, class: vecr, preferred-register: '' } 363 - { id: 3, class: vecr, preferred-register: '' } 364 - { id: 4, class: vecr, preferred-register: '' } 365 - { id: 5, class: gpr, preferred-register: '' } 366 - { id: 6, class: gpr, preferred-register: '' } 367 - { id: 7, class: vecr, preferred-register: '' } 368 - { id: 8, class: vecr, preferred-register: '' } 369liveins: 370fixedStack: 371stack: 372constants: 373body: | 374 ; ALL-LABEL: name: test_float 375 ; ALL: bb.0.entry: 376 ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000) 377 ; ALL: liveins: $edi, $xmm0, $xmm1 378 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi 379 ; ALL: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0 380 ; ALL: [[COPY2:%[0-9]+]]:fr32 = COPY [[COPY1]] 381 ; ALL: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1 382 ; ALL: [[COPY4:%[0-9]+]]:fr32 = COPY [[COPY3]] 383 ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags 384 ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags 385 ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags 386 ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags 387 ; ALL: JCC_1 %bb.2, 5, implicit $eflags 388 ; ALL: bb.1.cond.false: 389 ; ALL: successors: %bb.2(0x80000000) 390 ; ALL: bb.2.cond.end: 391 ; ALL: [[PHI:%[0-9]+]]:fr32 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0 392 ; ALL: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]] 393 ; ALL: $xmm0 = COPY [[COPY5]] 394 ; ALL: RET 0, implicit $xmm0 395 bb.1.entry: 396 successors: %bb.3(0x40000000), %bb.2(0x40000000) 397 liveins: $edi, $xmm0, $xmm1 398 399 %0:gpr(s32) = COPY $edi 400 %3:vecr(s128) = COPY $xmm0 401 %1:vecr(s32) = G_TRUNC %3(s128) 402 %4:vecr(s128) = COPY $xmm1 403 %2:vecr(s32) = G_TRUNC %4(s128) 404 %5:gpr(s32) = G_CONSTANT i32 0 405 %9:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5 406 %6:gpr(s1) = G_TRUNC %9(s8) 407 G_BRCOND %6(s1), %bb.3 408 409 bb.2.cond.false: 410 successors: %bb.3(0x80000000) 411 412 bb.3.cond.end: 413 %7:vecr(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1 414 %8:vecr(s128) = G_ANYEXT %7(s32) 415 $xmm0 = COPY %8(s128) 416 RET 0, implicit $xmm0 417 418... 419--- 420name: test_double 421alignment: 16 422legalized: true 423regBankSelected: true 424tracksRegLiveness: true 425registers: 426 - { id: 0, class: gpr, preferred-register: '' } 427 - { id: 1, class: vecr, preferred-register: '' } 428 - { id: 2, class: vecr, preferred-register: '' } 429 - { id: 3, class: vecr, preferred-register: '' } 430 - { id: 4, class: vecr, preferred-register: '' } 431 - { id: 5, class: gpr, preferred-register: '' } 432 - { id: 6, class: gpr, preferred-register: '' } 433 - { id: 7, class: vecr, preferred-register: '' } 434 - { id: 8, class: vecr, preferred-register: '' } 435body: | 436 ; ALL-LABEL: name: test_double 437 ; ALL: bb.0.entry: 438 ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000) 439 ; ALL: liveins: $edi, $xmm0, $xmm1 440 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi 441 ; ALL: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0 442 ; ALL: [[COPY2:%[0-9]+]]:fr64 = COPY [[COPY1]] 443 ; ALL: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1 444 ; ALL: [[COPY4:%[0-9]+]]:fr64 = COPY [[COPY3]] 445 ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags 446 ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags 447 ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags 448 ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags 449 ; ALL: JCC_1 %bb.2, 5, implicit $eflags 450 ; ALL: bb.1.cond.false: 451 ; ALL: successors: %bb.2(0x80000000) 452 ; ALL: bb.2.cond.end: 453 ; ALL: [[PHI:%[0-9]+]]:fr64 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0 454 ; ALL: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]] 455 ; ALL: $xmm0 = COPY [[COPY5]] 456 ; ALL: RET 0, implicit $xmm0 457 bb.1.entry: 458 successors: %bb.3(0x40000000), %bb.2(0x40000000) 459 liveins: $edi, $xmm0, $xmm1 460 461 %0:gpr(s32) = COPY $edi 462 %3:vecr(s128) = COPY $xmm0 463 %1:vecr(s64) = G_TRUNC %3(s128) 464 %4:vecr(s128) = COPY $xmm1 465 %2:vecr(s64) = G_TRUNC %4(s128) 466 %5:gpr(s32) = G_CONSTANT i32 0 467 %9:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5 468 %6:gpr(s1) = G_TRUNC %9(s8) 469 G_BRCOND %6(s1), %bb.3 470 471 bb.2.cond.false: 472 successors: %bb.3(0x80000000) 473 474 bb.3.cond.end: 475 %7:vecr(s64) = G_PHI %2(s64), %bb.2, %1(s64), %bb.1 476 %8:vecr(s128) = G_ANYEXT %7(s64) 477 $xmm0 = COPY %8(s128) 478 RET 0, implicit $xmm0 479 480... 481