1# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,SSE2 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX1 3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX512VL 4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX512BWVL 5 6--- | 7 define <16 x i8> @test_sub_v16i8(<16 x i8> %arg1, <16 x i8> %arg2) { 8 %ret = sub <16 x i8> %arg1, %arg2 9 ret <16 x i8> %ret 10 } 11 12 define <8 x i16> @test_sub_v8i16(<8 x i16> %arg1, <8 x i16> %arg2) { 13 %ret = sub <8 x i16> %arg1, %arg2 14 ret <8 x i16> %ret 15 } 16 17 define <4 x i32> @test_sub_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) { 18 %ret = sub <4 x i32> %arg1, %arg2 19 ret <4 x i32> %ret 20 } 21 22 define <2 x i64> @test_sub_v2i64(<2 x i64> %arg1, <2 x i64> %arg2) { 23 %ret = sub <2 x i64> %arg1, %arg2 24 ret <2 x i64> %ret 25 } 26 27... 28--- 29name: test_sub_v16i8 30# ALL-LABEL: name: test_sub_v16i8 31alignment: 16 32legalized: true 33regBankSelected: true 34registers: 35 - { id: 0, class: vecr } 36 - { id: 1, class: vecr } 37 - { id: 2, class: vecr } 38# SSE2: %2:vr128 = PSUBBrr %0, %1 39# 40# AVX1: %2:vr128 = VPSUBBrr %0, %1 41# 42# AVX512VL: %2:vr128 = VPSUBBrr %0, %1 43# 44# AVX512BWVL: %2:vr128x = VPSUBBZ128rr %0, %1 45body: | 46 bb.1 (%ir-block.0): 47 liveins: $xmm0, $xmm1 48 49 %0(<16 x s8>) = COPY $xmm0 50 %1(<16 x s8>) = COPY $xmm1 51 %2(<16 x s8>) = G_SUB %0, %1 52 $xmm0 = COPY %2(<16 x s8>) 53 RET 0, implicit $xmm0 54 55... 56--- 57name: test_sub_v8i16 58# ALL-LABEL: name: test_sub_v8i16 59alignment: 16 60legalized: true 61regBankSelected: true 62registers: 63 - { id: 0, class: vecr } 64 - { id: 1, class: vecr } 65 - { id: 2, class: vecr } 66# SSE2: %2:vr128 = PSUBWrr %0, %1 67# 68# AVX1: %2:vr128 = VPSUBWrr %0, %1 69# 70# AVX512VL: %2:vr128 = VPSUBWrr %0, %1 71# 72# AVX512BWVL: %2:vr128x = VPSUBWZ128rr %0, %1 73body: | 74 bb.1 (%ir-block.0): 75 liveins: $xmm0, $xmm1 76 77 %0(<8 x s16>) = COPY $xmm0 78 %1(<8 x s16>) = COPY $xmm1 79 %2(<8 x s16>) = G_SUB %0, %1 80 $xmm0 = COPY %2(<8 x s16>) 81 RET 0, implicit $xmm0 82 83... 84--- 85name: test_sub_v4i32 86# ALL-LABEL: name: test_sub_v4i32 87alignment: 16 88legalized: true 89regBankSelected: true 90registers: 91 - { id: 0, class: vecr } 92 - { id: 1, class: vecr } 93 - { id: 2, class: vecr } 94# SSE2: %2:vr128 = PSUBDrr %0, %1 95# 96# AVX1: %2:vr128 = VPSUBDrr %0, %1 97# 98# AVX512VL: %2:vr128x = VPSUBDZ128rr %0, %1 99# 100# AVX512BWVL: %2:vr128x = VPSUBDZ128rr %0, %1 101body: | 102 bb.1 (%ir-block.0): 103 liveins: $xmm0, $xmm1 104 105 %0(<4 x s32>) = COPY $xmm0 106 %1(<4 x s32>) = COPY $xmm1 107 %2(<4 x s32>) = G_SUB %0, %1 108 $xmm0 = COPY %2(<4 x s32>) 109 RET 0, implicit $xmm0 110 111... 112--- 113name: test_sub_v2i64 114# ALL-LABEL: name: test_sub_v2i64 115alignment: 16 116legalized: true 117regBankSelected: true 118registers: 119 - { id: 0, class: vecr } 120 - { id: 1, class: vecr } 121 - { id: 2, class: vecr } 122# SSE2: %2:vr128 = PSUBQrr %0, %1 123# 124# AVX1: %2:vr128 = VPSUBQrr %0, %1 125# 126# AVX512VL: %2:vr128x = VPSUBQZ128rr %0, %1 127# 128# AVX512BWVL: %2:vr128x = VPSUBQZ128rr %0, %1 129body: | 130 bb.1 (%ir-block.0): 131 liveins: $xmm0, $xmm1 132 133 %0(<2 x s64>) = COPY $xmm0 134 %1(<2 x s64>) = COPY $xmm1 135 %2(<2 x s64>) = G_SUB %0, %1 136 $xmm0 = COPY %2(<2 x s64>) 137 RET 0, implicit $xmm0 138 139... 140