1# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX2 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL 3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BWVL 4 5--- | 6 define <32 x i8> @test_sub_v32i8(<32 x i8> %arg1, <32 x i8> %arg2) { 7 %ret = sub <32 x i8> %arg1, %arg2 8 ret <32 x i8> %ret 9 } 10 11 define <16 x i16> @test_sub_v16i16(<16 x i16> %arg1, <16 x i16> %arg2) { 12 %ret = sub <16 x i16> %arg1, %arg2 13 ret <16 x i16> %ret 14 } 15 16 define <8 x i32> @test_sub_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) { 17 %ret = sub <8 x i32> %arg1, %arg2 18 ret <8 x i32> %ret 19 } 20 21 define <4 x i64> @test_sub_v4i64(<4 x i64> %arg1, <4 x i64> %arg2) { 22 %ret = sub <4 x i64> %arg1, %arg2 23 ret <4 x i64> %ret 24 } 25... 26--- 27name: test_sub_v32i8 28# ALL-LABEL: name: test_sub_v32i8 29alignment: 16 30legalized: true 31regBankSelected: true 32registers: 33 - { id: 0, class: vecr } 34 - { id: 1, class: vecr } 35 - { id: 2, class: vecr } 36# AVX2: %2:vr256 = VPSUBBYrr %0, %1 37# 38# AVX512VL: %2:vr256 = VPSUBBYrr %0, %1 39# 40# AVX512BWVL: %2:vr256x = VPSUBBZ256rr %0, %1 41body: | 42 bb.1 (%ir-block.0): 43 liveins: $ymm0, $ymm1 44 45 %0(<32 x s8>) = COPY $ymm0 46 %1(<32 x s8>) = COPY $ymm1 47 %2(<32 x s8>) = G_SUB %0, %1 48 $ymm0 = COPY %2(<32 x s8>) 49 RET 0, implicit $ymm0 50 51... 52--- 53name: test_sub_v16i16 54# ALL-LABEL: name: test_sub_v16i16 55alignment: 16 56legalized: true 57regBankSelected: true 58registers: 59 - { id: 0, class: vecr } 60 - { id: 1, class: vecr } 61 - { id: 2, class: vecr } 62# AVX2: %2:vr256 = VPSUBWYrr %0, %1 63# 64# AVX512VL: %2:vr256 = VPSUBWYrr %0, %1 65# 66# AVX512BWVL: %2:vr256x = VPSUBWZ256rr %0, %1 67body: | 68 bb.1 (%ir-block.0): 69 liveins: $ymm0, $ymm1 70 71 %0(<16 x s16>) = COPY $ymm0 72 %1(<16 x s16>) = COPY $ymm1 73 %2(<16 x s16>) = G_SUB %0, %1 74 $ymm0 = COPY %2(<16 x s16>) 75 RET 0, implicit $ymm0 76 77... 78--- 79name: test_sub_v8i32 80# ALL-LABEL: name: test_sub_v8i32 81alignment: 16 82legalized: true 83regBankSelected: true 84registers: 85 - { id: 0, class: vecr } 86 - { id: 1, class: vecr } 87 - { id: 2, class: vecr } 88# AVX2: %2:vr256 = VPSUBDYrr %0, %1 89# 90# AVX512VL: %2:vr256x = VPSUBDZ256rr %0, %1 91# 92# AVX512BWVL: %2:vr256x = VPSUBDZ256rr %0, %1 93body: | 94 bb.1 (%ir-block.0): 95 liveins: $ymm0, $ymm1 96 97 %0(<8 x s32>) = COPY $ymm0 98 %1(<8 x s32>) = COPY $ymm1 99 %2(<8 x s32>) = G_SUB %0, %1 100 $ymm0 = COPY %2(<8 x s32>) 101 RET 0, implicit $ymm0 102 103... 104--- 105name: test_sub_v4i64 106# ALL-LABEL: name: test_sub_v4i64 107alignment: 16 108legalized: true 109regBankSelected: true 110registers: 111 - { id: 0, class: vecr } 112 - { id: 1, class: vecr } 113 - { id: 2, class: vecr } 114# AVX2: %2:vr256 = VPSUBQYrr %0, %1 115# 116# AVX512VL: %2:vr256x = VPSUBQZ256rr %0, %1 117# 118# AVX512BWVL: %2:vr256x = VPSUBQZ256rr %0, %1 119body: | 120 bb.1 (%ir-block.0): 121 liveins: $ymm0, $ymm1 122 123 %0(<4 x s64>) = COPY $ymm0 124 %1(<4 x s64>) = COPY $ymm1 125 %2(<4 x s64>) = G_SUB %0, %1 126 $ymm0 = COPY %2(<4 x s64>) 127 RET 0, implicit $ymm0 128 129... 130