1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -mattr=+avx512ifma | FileCheck %s --check-prefixes=CHECK,X86 3; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512ifma | FileCheck %s --check-prefixes=CHECK,X64 4 5; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/avx512ifma-builtins.c 6 7define <8 x i64> @test_mm512_madd52hi_epu64(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) { 8; CHECK-LABEL: test_mm512_madd52hi_epu64: 9; CHECK: # %bb.0: # %entry 10; CHECK-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 11; CHECK-NEXT: ret{{[l|q]}} 12entry: 13 %0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52h.uq.512(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) 14 ret <8 x i64> %0 15} 16 17define <8 x i64> @test_mm512_mask_madd52hi_epu64(<8 x i64> %__W, i8 zeroext %__M, <8 x i64> %__X, <8 x i64> %__Y) { 18; X86-LABEL: test_mm512_mask_madd52hi_epu64: 19; X86: # %bb.0: # %entry 20; X86-NEXT: movb {{[0-9]+}}(%esp), %al 21; X86-NEXT: kmovw %eax, %k1 22; X86-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 {%k1} 23; X86-NEXT: retl 24; 25; X64-LABEL: test_mm512_mask_madd52hi_epu64: 26; X64: # %bb.0: # %entry 27; X64-NEXT: kmovw %edi, %k1 28; X64-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 {%k1} 29; X64-NEXT: retq 30entry: 31 %0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52h.uq.512(<8 x i64> %__W, <8 x i64> %__X, <8 x i64> %__Y) 32 %1 = bitcast i8 %__M to <8 x i1> 33 %2 = select <8 x i1> %1, <8 x i64> %0, <8 x i64> %__W 34 ret <8 x i64> %2 35} 36 37define <8 x i64> @test_mm512_maskz_madd52hi_epu64(i8 zeroext %__M, <8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) { 38; X86-LABEL: test_mm512_maskz_madd52hi_epu64: 39; X86: # %bb.0: # %entry 40; X86-NEXT: movb {{[0-9]+}}(%esp), %al 41; X86-NEXT: kmovw %eax, %k1 42; X86-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 {%k1} {z} 43; X86-NEXT: retl 44; 45; X64-LABEL: test_mm512_maskz_madd52hi_epu64: 46; X64: # %bb.0: # %entry 47; X64-NEXT: kmovw %edi, %k1 48; X64-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 {%k1} {z} 49; X64-NEXT: retq 50entry: 51 %0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52h.uq.512(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) 52 %1 = bitcast i8 %__M to <8 x i1> 53 %2 = select <8 x i1> %1, <8 x i64> %0, <8 x i64> zeroinitializer 54 ret <8 x i64> %2 55} 56 57define <8 x i64> @test_mm512_madd52lo_epu64(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) { 58; CHECK-LABEL: test_mm512_madd52lo_epu64: 59; CHECK: # %bb.0: # %entry 60; CHECK-NEXT: vpmadd52luq %zmm2, %zmm1, %zmm0 61; CHECK-NEXT: ret{{[l|q]}} 62entry: 63 %0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52l.uq.512(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) 64 ret <8 x i64> %0 65} 66 67define <8 x i64> @test_mm512_mask_madd52lo_epu64(<8 x i64> %__W, i8 zeroext %__M, <8 x i64> %__X, <8 x i64> %__Y) { 68; X86-LABEL: test_mm512_mask_madd52lo_epu64: 69; X86: # %bb.0: # %entry 70; X86-NEXT: movb {{[0-9]+}}(%esp), %al 71; X86-NEXT: kmovw %eax, %k1 72; X86-NEXT: vpmadd52luq %zmm2, %zmm1, %zmm0 {%k1} 73; X86-NEXT: retl 74; 75; X64-LABEL: test_mm512_mask_madd52lo_epu64: 76; X64: # %bb.0: # %entry 77; X64-NEXT: kmovw %edi, %k1 78; X64-NEXT: vpmadd52luq %zmm2, %zmm1, %zmm0 {%k1} 79; X64-NEXT: retq 80entry: 81 %0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52l.uq.512(<8 x i64> %__W, <8 x i64> %__X, <8 x i64> %__Y) 82 %1 = bitcast i8 %__M to <8 x i1> 83 %2 = select <8 x i1> %1, <8 x i64> %0, <8 x i64> %__W 84 ret <8 x i64> %2 85} 86 87define <8 x i64> @test_mm512_maskz_madd52lo_epu64(i8 zeroext %__M, <8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) { 88; X86-LABEL: test_mm512_maskz_madd52lo_epu64: 89; X86: # %bb.0: # %entry 90; X86-NEXT: movb {{[0-9]+}}(%esp), %al 91; X86-NEXT: kmovw %eax, %k1 92; X86-NEXT: vpmadd52luq %zmm2, %zmm1, %zmm0 {%k1} {z} 93; X86-NEXT: retl 94; 95; X64-LABEL: test_mm512_maskz_madd52lo_epu64: 96; X64: # %bb.0: # %entry 97; X64-NEXT: kmovw %edi, %k1 98; X64-NEXT: vpmadd52luq %zmm2, %zmm1, %zmm0 {%k1} {z} 99; X64-NEXT: retq 100entry: 101 %0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52l.uq.512(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) 102 %1 = bitcast i8 %__M to <8 x i1> 103 %2 = select <8 x i1> %1, <8 x i64> %0, <8 x i64> zeroinitializer 104 ret <8 x i64> %2 105} 106 107declare <8 x i64> @llvm.x86.avx512.vpmadd52h.uq.512(<8 x i64>, <8 x i64>, <8 x i64>) 108declare <8 x i64> @llvm.x86.avx512.vpmadd52l.uq.512(<8 x i64>, <8 x i64>, <8 x i64>) 109