1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -mattr=+avx512cd,+avx512vl | FileCheck %s 3; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512cd,+avx512vl | FileCheck %s 4 5define <2 x i64> @test_mm_broadcastmb_epi64(<2 x i64> %a, <2 x i64> %b) { 6; CHECK-LABEL: test_mm_broadcastmb_epi64: 7; CHECK: # %bb.0: # %entry 8; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 9; CHECK-NEXT: vpbroadcastmb2q %k0, %xmm0 10; CHECK-NEXT: ret{{[l|q]}} 11entry: 12 %0 = bitcast <2 x i64> %a to <4 x i32> 13 %1 = bitcast <2 x i64> %b to <4 x i32> 14 %2 = icmp eq <4 x i32> %0, %1 15 %3 = shufflevector <4 x i1> %2, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 16 %4 = bitcast <8 x i1> %3 to i8 17 %conv.i = zext i8 %4 to i64 18 %vecinit.i.i = insertelement <2 x i64> undef, i64 %conv.i, i32 0 19 %vecinit1.i.i = shufflevector <2 x i64> %vecinit.i.i, <2 x i64> undef, <2 x i32> zeroinitializer 20 ret <2 x i64> %vecinit1.i.i 21} 22 23define <4 x i64> @test_mm256_broadcastmb_epi64(<4 x i64> %a, <4 x i64> %b) { 24; CHECK-LABEL: test_mm256_broadcastmb_epi64: 25; CHECK: # %bb.0: # %entry 26; CHECK-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 27; CHECK-NEXT: vpbroadcastmb2q %k0, %ymm0 28; CHECK-NEXT: ret{{[l|q]}} 29entry: 30 %0 = icmp eq <4 x i64> %a, %b 31 %1 = shufflevector <4 x i1> %0, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 32 %2 = bitcast <8 x i1> %1 to i8 33 %conv.i = zext i8 %2 to i64 34 %vecinit.i.i = insertelement <4 x i64> undef, i64 %conv.i, i32 0 35 %vecinit3.i.i = shufflevector <4 x i64> %vecinit.i.i, <4 x i64> undef, <4 x i32> zeroinitializer 36 ret <4 x i64> %vecinit3.i.i 37} 38 39define <2 x i64> @test_mm_broadcastmw_epi32(<8 x i64> %a, <8 x i64> %b) { 40; CHECK-LABEL: test_mm_broadcastmw_epi32: 41; CHECK: # %bb.0: # %entry 42; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 43; CHECK-NEXT: vpbroadcastmw2d %k0, %xmm0 44; CHECK-NEXT: vzeroupper 45; CHECK-NEXT: ret{{[l|q]}} 46entry: 47 %0 = bitcast <8 x i64> %a to <16 x i32> 48 %1 = bitcast <8 x i64> %b to <16 x i32> 49 %2 = icmp eq <16 x i32> %0, %1 50 %3 = bitcast <16 x i1> %2 to i16 51 %conv.i = zext i16 %3 to i32 52 %vecinit.i.i = insertelement <4 x i32> undef, i32 %conv.i, i32 0 53 %vecinit3.i.i = shufflevector <4 x i32> %vecinit.i.i, <4 x i32> undef, <4 x i32> zeroinitializer 54 %4 = bitcast <4 x i32> %vecinit3.i.i to <2 x i64> 55 ret <2 x i64> %4 56} 57 58define <4 x i64> @test_mm256_broadcastmw_epi32(<8 x i64> %a, <8 x i64> %b) { 59; CHECK-LABEL: test_mm256_broadcastmw_epi32: 60; CHECK: # %bb.0: # %entry 61; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 62; CHECK-NEXT: vpbroadcastmw2d %k0, %ymm0 63; CHECK-NEXT: ret{{[l|q]}} 64entry: 65 %0 = bitcast <8 x i64> %a to <16 x i32> 66 %1 = bitcast <8 x i64> %b to <16 x i32> 67 %2 = icmp eq <16 x i32> %0, %1 68 %3 = bitcast <16 x i1> %2 to i16 69 %conv.i = zext i16 %3 to i32 70 %vecinit.i.i = insertelement <8 x i32> undef, i32 %conv.i, i32 0 71 %vecinit7.i.i = shufflevector <8 x i32> %vecinit.i.i, <8 x i32> undef, <8 x i32> zeroinitializer 72 %4 = bitcast <8 x i32> %vecinit7.i.i to <4 x i64> 73 ret <4 x i64> %4 74} 75 76 77