1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-windows-msvc19.11.0 | FileCheck %s 3 4; This matches the code produced by clang/lib/CodeGen/bittest-intrin.c 5 6@sink = global i8 0, align 1 7 8define void @test32(i32* %base, i32 %idx) { 9; CHECK-LABEL: test32: 10; CHECK: # %bb.0: # %entry 11; CHECK-NEXT: #APP 12; CHECK-NEXT: btl %edx, (%rcx) 13; CHECK-NEXT: #NO_APP 14; CHECK-NEXT: setb {{.*}}(%rip) 15; CHECK-NEXT: #APP 16; CHECK-NEXT: btcl %edx, (%rcx) 17; CHECK-NEXT: #NO_APP 18; CHECK-NEXT: setb {{.*}}(%rip) 19; CHECK-NEXT: #APP 20; CHECK-NEXT: btrl %edx, (%rcx) 21; CHECK-NEXT: #NO_APP 22; CHECK-NEXT: setb {{.*}}(%rip) 23; CHECK-NEXT: #APP 24; CHECK-NEXT: btsl %edx, (%rcx) 25; CHECK-NEXT: #NO_APP 26; CHECK-NEXT: setb {{.*}}(%rip) 27; CHECK-NEXT: #APP 28; CHECK-NEXT: lock btrl %edx, (%rcx) 29; CHECK-NEXT: #NO_APP 30; CHECK-NEXT: setb {{.*}}(%rip) 31; CHECK-NEXT: #APP 32; CHECK-NEXT: lock btsl %edx, (%rcx) 33; CHECK-NEXT: #NO_APP 34; CHECK-NEXT: setb {{.*}}(%rip) 35; CHECK-NEXT: #APP 36; CHECK-NEXT: lock btsl %edx, (%rcx) 37; CHECK-NEXT: #NO_APP 38; CHECK-NEXT: setb {{.*}}(%rip) 39; CHECK-NEXT: retq 40entry: 41 %0 = tail call i8 asm sideeffect "btl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx) 42 store volatile i8 %0, i8* @sink, align 1 43 %1 = tail call i8 asm sideeffect "btcl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx) 44 store volatile i8 %1, i8* @sink, align 1 45 %2 = tail call i8 asm sideeffect "btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx) 46 store volatile i8 %2, i8* @sink, align 1 47 %3 = tail call i8 asm sideeffect "btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx) 48 store volatile i8 %3, i8* @sink, align 1 49 %4 = tail call i8 asm sideeffect "lock btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx) 50 store volatile i8 %4, i8* @sink, align 1 51 %5 = tail call i8 asm sideeffect "lock btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx) 52 store volatile i8 %5, i8* @sink, align 1 53 %6 = tail call i8 asm sideeffect "lock btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx) 54 store volatile i8 %6, i8* @sink, align 1 55 ret void 56} 57 58; Function Attrs: nounwind uwtable 59define void @test64(i64* %base, i64 %idx) { 60; CHECK-LABEL: test64: 61; CHECK: # %bb.0: # %entry 62; CHECK-NEXT: #APP 63; CHECK-NEXT: btq %rdx, (%rcx) 64; CHECK-NEXT: #NO_APP 65; CHECK-NEXT: setb {{.*}}(%rip) 66; CHECK-NEXT: #APP 67; CHECK-NEXT: btcq %rdx, (%rcx) 68; CHECK-NEXT: #NO_APP 69; CHECK-NEXT: setb {{.*}}(%rip) 70; CHECK-NEXT: #APP 71; CHECK-NEXT: btrq %rdx, (%rcx) 72; CHECK-NEXT: #NO_APP 73; CHECK-NEXT: setb {{.*}}(%rip) 74; CHECK-NEXT: #APP 75; CHECK-NEXT: btsq %rdx, (%rcx) 76; CHECK-NEXT: #NO_APP 77; CHECK-NEXT: setb {{.*}}(%rip) 78; CHECK-NEXT: #APP 79; CHECK-NEXT: lock btrq %rdx, (%rcx) 80; CHECK-NEXT: #NO_APP 81; CHECK-NEXT: setb {{.*}}(%rip) 82; CHECK-NEXT: #APP 83; CHECK-NEXT: lock btsq %rdx, (%rcx) 84; CHECK-NEXT: #NO_APP 85; CHECK-NEXT: setb {{.*}}(%rip) 86; CHECK-NEXT: retq 87entry: 88 %0 = tail call i8 asm sideeffect "btq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx) 89 store volatile i8 %0, i8* @sink, align 1 90 %1 = tail call i8 asm sideeffect "btcq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx) 91 store volatile i8 %1, i8* @sink, align 1 92 %2 = tail call i8 asm sideeffect "btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx) 93 store volatile i8 %2, i8* @sink, align 1 94 %3 = tail call i8 asm sideeffect "btsq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx) 95 store volatile i8 %3, i8* @sink, align 1 96 %4 = tail call i8 asm sideeffect "lock btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx) 97 store volatile i8 %4, i8* @sink, align 1 98 %5 = tail call i8 asm sideeffect "lock btsq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx) 99 store volatile i8 %5, i8* @sink, align 1 100 ret void 101} 102