1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s --check-prefix=SSE41 3 4define double @test1_add(double %A, double %B) { 5; SSE41-LABEL: test1_add: 6; SSE41: # %bb.0: 7; SSE41-NEXT: paddd %xmm1, %xmm0 8; SSE41-NEXT: retq 9 %1 = bitcast double %A to <2 x i32> 10 %2 = bitcast double %B to <2 x i32> 11 %add = add <2 x i32> %1, %2 12 %3 = bitcast <2 x i32> %add to double 13 ret double %3 14} 15 16define double @test2_add(double %A, double %B) { 17; SSE41-LABEL: test2_add: 18; SSE41: # %bb.0: 19; SSE41-NEXT: paddw %xmm1, %xmm0 20; SSE41-NEXT: retq 21 %1 = bitcast double %A to <4 x i16> 22 %2 = bitcast double %B to <4 x i16> 23 %add = add <4 x i16> %1, %2 24 %3 = bitcast <4 x i16> %add to double 25 ret double %3 26} 27 28define double @test3_add(double %A, double %B) { 29; SSE41-LABEL: test3_add: 30; SSE41: # %bb.0: 31; SSE41-NEXT: paddb %xmm1, %xmm0 32; SSE41-NEXT: retq 33 %1 = bitcast double %A to <8 x i8> 34 %2 = bitcast double %B to <8 x i8> 35 %add = add <8 x i8> %1, %2 36 %3 = bitcast <8 x i8> %add to double 37 ret double %3 38} 39 40define double @test1_sub(double %A, double %B) { 41; SSE41-LABEL: test1_sub: 42; SSE41: # %bb.0: 43; SSE41-NEXT: psubd %xmm1, %xmm0 44; SSE41-NEXT: retq 45 %1 = bitcast double %A to <2 x i32> 46 %2 = bitcast double %B to <2 x i32> 47 %sub = sub <2 x i32> %1, %2 48 %3 = bitcast <2 x i32> %sub to double 49 ret double %3 50} 51 52define double @test2_sub(double %A, double %B) { 53; SSE41-LABEL: test2_sub: 54; SSE41: # %bb.0: 55; SSE41-NEXT: psubw %xmm1, %xmm0 56; SSE41-NEXT: retq 57 %1 = bitcast double %A to <4 x i16> 58 %2 = bitcast double %B to <4 x i16> 59 %sub = sub <4 x i16> %1, %2 60 %3 = bitcast <4 x i16> %sub to double 61 ret double %3 62} 63 64define double @test3_sub(double %A, double %B) { 65; SSE41-LABEL: test3_sub: 66; SSE41: # %bb.0: 67; SSE41-NEXT: psubb %xmm1, %xmm0 68; SSE41-NEXT: retq 69 %1 = bitcast double %A to <8 x i8> 70 %2 = bitcast double %B to <8 x i8> 71 %sub = sub <8 x i8> %1, %2 72 %3 = bitcast <8 x i8> %sub to double 73 ret double %3 74} 75 76define double @test1_mul(double %A, double %B) { 77; SSE41-LABEL: test1_mul: 78; SSE41: # %bb.0: 79; SSE41-NEXT: pmulld %xmm1, %xmm0 80; SSE41-NEXT: retq 81 %1 = bitcast double %A to <2 x i32> 82 %2 = bitcast double %B to <2 x i32> 83 %mul = mul <2 x i32> %1, %2 84 %3 = bitcast <2 x i32> %mul to double 85 ret double %3 86} 87 88define double @test2_mul(double %A, double %B) { 89; SSE41-LABEL: test2_mul: 90; SSE41: # %bb.0: 91; SSE41-NEXT: pmullw %xmm1, %xmm0 92; SSE41-NEXT: retq 93 %1 = bitcast double %A to <4 x i16> 94 %2 = bitcast double %B to <4 x i16> 95 %mul = mul <4 x i16> %1, %2 96 %3 = bitcast <4 x i16> %mul to double 97 ret double %3 98} 99 100; There is no legal ISD::MUL with type MVT::v16i8. 101define double @test3_mul(double %A, double %B) { 102; SSE41-LABEL: test3_mul: 103; SSE41: # %bb.0: 104; SSE41-NEXT: pmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero 105; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero 106; SSE41-NEXT: pmullw %xmm1, %xmm0 107; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] 108; SSE41-NEXT: retq 109 %1 = bitcast double %A to <8 x i8> 110 %2 = bitcast double %B to <8 x i8> 111 %mul = mul <8 x i8> %1, %2 112 %3 = bitcast <8 x i8> %mul to double 113 ret double %3 114} 115 116define double @test1_and(double %A, double %B) { 117; SSE41-LABEL: test1_and: 118; SSE41: # %bb.0: 119; SSE41-NEXT: andps %xmm1, %xmm0 120; SSE41-NEXT: retq 121 %1 = bitcast double %A to <2 x i32> 122 %2 = bitcast double %B to <2 x i32> 123 %and = and <2 x i32> %1, %2 124 %3 = bitcast <2 x i32> %and to double 125 ret double %3 126} 127 128define double @test2_and(double %A, double %B) { 129; SSE41-LABEL: test2_and: 130; SSE41: # %bb.0: 131; SSE41-NEXT: andps %xmm1, %xmm0 132; SSE41-NEXT: retq 133 %1 = bitcast double %A to <4 x i16> 134 %2 = bitcast double %B to <4 x i16> 135 %and = and <4 x i16> %1, %2 136 %3 = bitcast <4 x i16> %and to double 137 ret double %3 138} 139 140define double @test3_and(double %A, double %B) { 141; SSE41-LABEL: test3_and: 142; SSE41: # %bb.0: 143; SSE41-NEXT: andps %xmm1, %xmm0 144; SSE41-NEXT: retq 145 %1 = bitcast double %A to <8 x i8> 146 %2 = bitcast double %B to <8 x i8> 147 %and = and <8 x i8> %1, %2 148 %3 = bitcast <8 x i8> %and to double 149 ret double %3 150} 151 152define double @test1_or(double %A, double %B) { 153; SSE41-LABEL: test1_or: 154; SSE41: # %bb.0: 155; SSE41-NEXT: orps %xmm1, %xmm0 156; SSE41-NEXT: retq 157 %1 = bitcast double %A to <2 x i32> 158 %2 = bitcast double %B to <2 x i32> 159 %or = or <2 x i32> %1, %2 160 %3 = bitcast <2 x i32> %or to double 161 ret double %3 162} 163 164define double @test2_or(double %A, double %B) { 165; SSE41-LABEL: test2_or: 166; SSE41: # %bb.0: 167; SSE41-NEXT: orps %xmm1, %xmm0 168; SSE41-NEXT: retq 169 %1 = bitcast double %A to <4 x i16> 170 %2 = bitcast double %B to <4 x i16> 171 %or = or <4 x i16> %1, %2 172 %3 = bitcast <4 x i16> %or to double 173 ret double %3 174} 175 176define double @test3_or(double %A, double %B) { 177; SSE41-LABEL: test3_or: 178; SSE41: # %bb.0: 179; SSE41-NEXT: orps %xmm1, %xmm0 180; SSE41-NEXT: retq 181 %1 = bitcast double %A to <8 x i8> 182 %2 = bitcast double %B to <8 x i8> 183 %or = or <8 x i8> %1, %2 184 %3 = bitcast <8 x i8> %or to double 185 ret double %3 186} 187 188define double @test1_xor(double %A, double %B) { 189; SSE41-LABEL: test1_xor: 190; SSE41: # %bb.0: 191; SSE41-NEXT: xorps %xmm1, %xmm0 192; SSE41-NEXT: retq 193 %1 = bitcast double %A to <2 x i32> 194 %2 = bitcast double %B to <2 x i32> 195 %xor = xor <2 x i32> %1, %2 196 %3 = bitcast <2 x i32> %xor to double 197 ret double %3 198} 199 200define double @test2_xor(double %A, double %B) { 201; SSE41-LABEL: test2_xor: 202; SSE41: # %bb.0: 203; SSE41-NEXT: xorps %xmm1, %xmm0 204; SSE41-NEXT: retq 205 %1 = bitcast double %A to <4 x i16> 206 %2 = bitcast double %B to <4 x i16> 207 %xor = xor <4 x i16> %1, %2 208 %3 = bitcast <4 x i16> %xor to double 209 ret double %3 210} 211 212define double @test3_xor(double %A, double %B) { 213; SSE41-LABEL: test3_xor: 214; SSE41: # %bb.0: 215; SSE41-NEXT: xorps %xmm1, %xmm0 216; SSE41-NEXT: retq 217 %1 = bitcast double %A to <8 x i8> 218 %2 = bitcast double %B to <8 x i8> 219 %xor = xor <8 x i8> %1, %2 220 %3 = bitcast <8 x i8> %xor to double 221 ret double %3 222} 223 224define double @test_fadd(double %A, double %B) { 225; SSE41-LABEL: test_fadd: 226; SSE41: # %bb.0: 227; SSE41-NEXT: addps %xmm1, %xmm0 228; SSE41-NEXT: retq 229 %1 = bitcast double %A to <2 x float> 230 %2 = bitcast double %B to <2 x float> 231 %add = fadd <2 x float> %1, %2 232 %3 = bitcast <2 x float> %add to double 233 ret double %3 234} 235 236define double @test_fsub(double %A, double %B) { 237; SSE41-LABEL: test_fsub: 238; SSE41: # %bb.0: 239; SSE41-NEXT: subps %xmm1, %xmm0 240; SSE41-NEXT: retq 241 %1 = bitcast double %A to <2 x float> 242 %2 = bitcast double %B to <2 x float> 243 %sub = fsub <2 x float> %1, %2 244 %3 = bitcast <2 x float> %sub to double 245 ret double %3 246} 247 248define double @test_fmul(double %A, double %B) { 249; SSE41-LABEL: test_fmul: 250; SSE41: # %bb.0: 251; SSE41-NEXT: mulps %xmm1, %xmm0 252; SSE41-NEXT: retq 253 %1 = bitcast double %A to <2 x float> 254 %2 = bitcast double %B to <2 x float> 255 %mul = fmul <2 x float> %1, %2 256 %3 = bitcast <2 x float> %mul to double 257 ret double %3 258} 259 260