1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE 5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX 6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX 7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX 8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX 9 10declare i32 @llvm.sadd.sat.i32 (i32, i32) 11declare i64 @llvm.sadd.sat.i64 (i64, i64) 12declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) 13 14; fold (sadd_sat x, undef) -> -1 15define i32 @combine_undef_i32(i32 %a0) { 16; CHECK-LABEL: combine_undef_i32: 17; CHECK: # %bb.0: 18; CHECK-NEXT: movl $-1, %eax 19; CHECK-NEXT: retq 20 %res = call i32 @llvm.sadd.sat.i32(i32 %a0, i32 undef) 21 ret i32 %res 22} 23 24define <8 x i16> @combine_undef_v8i16(<8 x i16> %a0) { 25; SSE-LABEL: combine_undef_v8i16: 26; SSE: # %bb.0: 27; SSE-NEXT: pcmpeqd %xmm0, %xmm0 28; SSE-NEXT: retq 29; 30; AVX-LABEL: combine_undef_v8i16: 31; AVX: # %bb.0: 32; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 33; AVX-NEXT: retq 34 %res = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> undef, <8 x i16> %a0) 35 ret <8 x i16> %res 36} 37 38; fold (sadd_sat c1, c2) -> c3 39define i32 @combine_constfold_i32() { 40; CHECK-LABEL: combine_constfold_i32: 41; CHECK: # %bb.0: 42; CHECK-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 43; CHECK-NEXT: retq 44 %res = call i32 @llvm.sadd.sat.i32(i32 2147483647, i32 100) 45 ret i32 %res 46} 47 48define <8 x i16> @combine_constfold_v8i16() { 49; SSE-LABEL: combine_constfold_v8i16: 50; SSE: # %bb.0: 51; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,0,256,65534,0,65280,32768,0] 52; SSE-NEXT: retq 53; 54; AVX-LABEL: combine_constfold_v8i16: 55; AVX: # %bb.0: 56; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,0,256,65534,0,65280,32768,0] 57; AVX-NEXT: retq 58 %res = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> <i16 0, i16 1, i16 255, i16 65535, i16 -1, i16 -255, i16 -32760, i16 1>, <8 x i16> <i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 -10, i16 65535>) 59 ret <8 x i16> %res 60} 61 62define <8 x i16> @combine_constfold_undef_v8i16() { 63; SSE-LABEL: combine_constfold_undef_v8i16: 64; SSE: # %bb.0: 65; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65535,65535,65534,0,65280,32768,0] 66; SSE-NEXT: retq 67; 68; AVX-LABEL: combine_constfold_undef_v8i16: 69; AVX: # %bb.0: 70; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65535,65535,65534,0,65280,32768,0] 71; AVX-NEXT: retq 72 %res = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> <i16 undef, i16 1, i16 undef, i16 65535, i16 -1, i16 -255, i16 -32760, i16 1>, <8 x i16> <i16 1, i16 undef, i16 undef, i16 65535, i16 1, i16 65535, i16 -10, i16 65535>) 73 ret <8 x i16> %res 74} 75 76; fold (sadd_sat c, x) -> (sadd_sat x, c) 77define i32 @combine_constant_i32(i32 %a0) { 78; CHECK-LABEL: combine_constant_i32: 79; CHECK: # %bb.0: 80; CHECK-NEXT: xorl %eax, %eax 81; CHECK-NEXT: movl %edi, %ecx 82; CHECK-NEXT: incl %ecx 83; CHECK-NEXT: setns %al 84; CHECK-NEXT: addl $2147483647, %eax # imm = 0x7FFFFFFF 85; CHECK-NEXT: incl %edi 86; CHECK-NEXT: cmovnol %edi, %eax 87; CHECK-NEXT: retq 88 %res = call i32 @llvm.sadd.sat.i32(i32 1, i32 %a0) 89 ret i32 %res 90} 91 92define <8 x i16> @combine_constant_v8i16(<8 x i16> %a0) { 93; SSE-LABEL: combine_constant_v8i16: 94; SSE: # %bb.0: 95; SSE-NEXT: paddsw {{.*}}(%rip), %xmm0 96; SSE-NEXT: retq 97; 98; AVX-LABEL: combine_constant_v8i16: 99; AVX: # %bb.0: 100; AVX-NEXT: vpaddsw {{.*}}(%rip), %xmm0, %xmm0 101; AVX-NEXT: retq 102 %res = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %a0) 103 ret <8 x i16> %res 104} 105 106; fold (sadd_sat c, 0) -> x 107define i32 @combine_zero_i32(i32 %a0) { 108; CHECK-LABEL: combine_zero_i32: 109; CHECK: # %bb.0: 110; CHECK-NEXT: movl %edi, %eax 111; CHECK-NEXT: retq 112 %1 = call i32 @llvm.sadd.sat.i32(i32 %a0, i32 0) 113 ret i32 %1 114} 115 116define <8 x i16> @combine_zero_v8i16(<8 x i16> %a0) { 117; CHECK-LABEL: combine_zero_v8i16: 118; CHECK: # %bb.0: 119; CHECK-NEXT: retq 120 %1 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %a0, <8 x i16> zeroinitializer) 121 ret <8 x i16> %1 122} 123 124; fold (sadd_sat x, y) -> (add x, y) iff no overflow 125define i32 @combine_no_overflow_i32(i32 %a0, i32 %a1) { 126; CHECK-LABEL: combine_no_overflow_i32: 127; CHECK: # %bb.0: 128; CHECK-NEXT: sarl $16, %edi 129; CHECK-NEXT: shrl $16, %esi 130; CHECK-NEXT: xorl %eax, %eax 131; CHECK-NEXT: movl %edi, %ecx 132; CHECK-NEXT: addl %esi, %ecx 133; CHECK-NEXT: setns %al 134; CHECK-NEXT: addl $2147483647, %eax # imm = 0x7FFFFFFF 135; CHECK-NEXT: addl %edi, %esi 136; CHECK-NEXT: cmovnol %esi, %eax 137; CHECK-NEXT: retq 138 %1 = ashr i32 %a0, 16 139 %2 = lshr i32 %a1, 16 140 %3 = call i32 @llvm.sadd.sat.i32(i32 %1, i32 %2) 141 ret i32 %3 142} 143 144define <8 x i16> @combine_no_overflow_v8i16(<8 x i16> %a0, <8 x i16> %a1) { 145; SSE-LABEL: combine_no_overflow_v8i16: 146; SSE: # %bb.0: 147; SSE-NEXT: psraw $10, %xmm0 148; SSE-NEXT: psrlw $10, %xmm1 149; SSE-NEXT: paddsw %xmm1, %xmm0 150; SSE-NEXT: retq 151; 152; AVX-LABEL: combine_no_overflow_v8i16: 153; AVX: # %bb.0: 154; AVX-NEXT: vpsraw $10, %xmm0, %xmm0 155; AVX-NEXT: vpsrlw $10, %xmm1, %xmm1 156; AVX-NEXT: vpaddsw %xmm1, %xmm0, %xmm0 157; AVX-NEXT: retq 158 %1 = ashr <8 x i16> %a0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10> 159 %2 = lshr <8 x i16> %a1, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10> 160 %3 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %1, <8 x i16> %2) 161 ret <8 x i16> %3 162} 163