1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -O0 | FileCheck %s --check-prefix=SSE 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -O0 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -mattr=avx | FileCheck %s --check-prefix=AVX 5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -fast-isel -fast-isel-abort=1 -mattr=avx | FileCheck %s --check-prefix=AVX 6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -mattr=avx512f | FileCheck %s --check-prefix=AVX512 7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -fast-isel -fast-isel-abort=1 -mattr=avx512f | FileCheck %s --check-prefix=AVX512 8 9; Test all cmp predicates that can be used with SSE. 10 11define float @select_fcmp_oeq_f32(float %a, float %b, float %c, float %d) { 12; SSE-LABEL: select_fcmp_oeq_f32: 13; SSE: # %bb.0: 14; SSE-NEXT: cmpeqss %xmm1, %xmm0 15; SSE-NEXT: movaps %xmm0, %xmm1 16; SSE-NEXT: andps %xmm2, %xmm1 17; SSE-NEXT: andnps %xmm3, %xmm0 18; SSE-NEXT: orps %xmm1, %xmm0 19; SSE-NEXT: retq 20; 21; AVX-LABEL: select_fcmp_oeq_f32: 22; AVX: # %bb.0: 23; AVX-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0 24; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 25; AVX-NEXT: retq 26; 27; AVX512-LABEL: select_fcmp_oeq_f32: 28; AVX512: # %bb.0: 29; AVX512-NEXT: vcmpeqss %xmm1, %xmm0, %k1 30; AVX512-NEXT: vmovss %xmm2, %xmm3, %xmm3 {%k1} 31; AVX512-NEXT: vmovaps %xmm3, %xmm0 32; AVX512-NEXT: retq 33 %1 = fcmp oeq float %a, %b 34 %2 = select i1 %1, float %c, float %d 35 ret float %2 36} 37 38define double @select_fcmp_oeq_f64(double %a, double %b, double %c, double %d) { 39; SSE-LABEL: select_fcmp_oeq_f64: 40; SSE: # %bb.0: 41; SSE-NEXT: cmpeqsd %xmm1, %xmm0 42; SSE-NEXT: movaps %xmm0, %xmm1 43; SSE-NEXT: andpd %xmm2, %xmm1 44; SSE-NEXT: andnpd %xmm3, %xmm0 45; SSE-NEXT: orpd %xmm1, %xmm0 46; SSE-NEXT: retq 47; 48; AVX-LABEL: select_fcmp_oeq_f64: 49; AVX: # %bb.0: 50; AVX-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 51; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0 52; AVX-NEXT: retq 53; 54; AVX512-LABEL: select_fcmp_oeq_f64: 55; AVX512: # %bb.0: 56; AVX512-NEXT: vcmpeqsd %xmm1, %xmm0, %k1 57; AVX512-NEXT: vmovsd %xmm2, %xmm3, %xmm3 {%k1} 58; AVX512-NEXT: vmovapd %xmm3, %xmm0 59; AVX512-NEXT: retq 60 %1 = fcmp oeq double %a, %b 61 %2 = select i1 %1, double %c, double %d 62 ret double %2 63} 64 65define float @select_fcmp_ogt_f32(float %a, float %b, float %c, float %d) { 66; SSE-LABEL: select_fcmp_ogt_f32: 67; SSE: # %bb.0: 68; SSE-NEXT: movss %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill 69; SSE-NEXT: movaps %xmm0, %xmm1 70; SSE-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload 71; SSE-NEXT: # xmm0 = mem[0],zero,zero,zero 72; SSE-NEXT: cmpltss %xmm1, %xmm0 73; SSE-NEXT: movaps %xmm0, %xmm1 74; SSE-NEXT: andps %xmm2, %xmm1 75; SSE-NEXT: andnps %xmm3, %xmm0 76; SSE-NEXT: orps %xmm1, %xmm0 77; SSE-NEXT: retq 78; 79; AVX-LABEL: select_fcmp_ogt_f32: 80; AVX: # %bb.0: 81; AVX-NEXT: vcmpltss %xmm0, %xmm1, %xmm0 82; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 83; AVX-NEXT: retq 84; 85; AVX512-LABEL: select_fcmp_ogt_f32: 86; AVX512: # %bb.0: 87; AVX512-NEXT: vcmpltss %xmm0, %xmm1, %k1 88; AVX512-NEXT: vmovss %xmm2, %xmm3, %xmm3 {%k1} 89; AVX512-NEXT: vmovaps %xmm3, %xmm0 90; AVX512-NEXT: retq 91 %1 = fcmp ogt float %a, %b 92 %2 = select i1 %1, float %c, float %d 93 ret float %2 94} 95 96define double @select_fcmp_ogt_f64(double %a, double %b, double %c, double %d) { 97; SSE-LABEL: select_fcmp_ogt_f64: 98; SSE: # %bb.0: 99; SSE-NEXT: movsd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill 100; SSE-NEXT: movaps %xmm0, %xmm1 101; SSE-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload 102; SSE-NEXT: # xmm0 = mem[0],zero 103; SSE-NEXT: cmpltsd %xmm1, %xmm0 104; SSE-NEXT: movaps %xmm0, %xmm1 105; SSE-NEXT: andpd %xmm2, %xmm1 106; SSE-NEXT: andnpd %xmm3, %xmm0 107; SSE-NEXT: orpd %xmm1, %xmm0 108; SSE-NEXT: retq 109; 110; AVX-LABEL: select_fcmp_ogt_f64: 111; AVX: # %bb.0: 112; AVX-NEXT: vcmpltsd %xmm0, %xmm1, %xmm0 113; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0 114; AVX-NEXT: retq 115; 116; AVX512-LABEL: select_fcmp_ogt_f64: 117; AVX512: # %bb.0: 118; AVX512-NEXT: vcmpltsd %xmm0, %xmm1, %k1 119; AVX512-NEXT: vmovsd %xmm2, %xmm3, %xmm3 {%k1} 120; AVX512-NEXT: vmovapd %xmm3, %xmm0 121; AVX512-NEXT: retq 122 %1 = fcmp ogt double %a, %b 123 %2 = select i1 %1, double %c, double %d 124 ret double %2 125} 126 127define float @select_fcmp_oge_f32(float %a, float %b, float %c, float %d) { 128; SSE-LABEL: select_fcmp_oge_f32: 129; SSE: # %bb.0: 130; SSE-NEXT: movss %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill 131; SSE-NEXT: movaps %xmm0, %xmm1 132; SSE-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload 133; SSE-NEXT: # xmm0 = mem[0],zero,zero,zero 134; SSE-NEXT: cmpless %xmm1, %xmm0 135; SSE-NEXT: movaps %xmm0, %xmm1 136; SSE-NEXT: andps %xmm2, %xmm1 137; SSE-NEXT: andnps %xmm3, %xmm0 138; SSE-NEXT: orps %xmm1, %xmm0 139; SSE-NEXT: retq 140; 141; AVX-LABEL: select_fcmp_oge_f32: 142; AVX: # %bb.0: 143; AVX-NEXT: vcmpless %xmm0, %xmm1, %xmm0 144; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 145; AVX-NEXT: retq 146; 147; AVX512-LABEL: select_fcmp_oge_f32: 148; AVX512: # %bb.0: 149; AVX512-NEXT: vcmpless %xmm0, %xmm1, %k1 150; AVX512-NEXT: vmovss %xmm2, %xmm3, %xmm3 {%k1} 151; AVX512-NEXT: vmovaps %xmm3, %xmm0 152; AVX512-NEXT: retq 153 %1 = fcmp oge float %a, %b 154 %2 = select i1 %1, float %c, float %d 155 ret float %2 156} 157 158define double @select_fcmp_oge_f64(double %a, double %b, double %c, double %d) { 159; SSE-LABEL: select_fcmp_oge_f64: 160; SSE: # %bb.0: 161; SSE-NEXT: movsd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill 162; SSE-NEXT: movaps %xmm0, %xmm1 163; SSE-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload 164; SSE-NEXT: # xmm0 = mem[0],zero 165; SSE-NEXT: cmplesd %xmm1, %xmm0 166; SSE-NEXT: movaps %xmm0, %xmm1 167; SSE-NEXT: andpd %xmm2, %xmm1 168; SSE-NEXT: andnpd %xmm3, %xmm0 169; SSE-NEXT: orpd %xmm1, %xmm0 170; SSE-NEXT: retq 171; 172; AVX-LABEL: select_fcmp_oge_f64: 173; AVX: # %bb.0: 174; AVX-NEXT: vcmplesd %xmm0, %xmm1, %xmm0 175; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0 176; AVX-NEXT: retq 177; 178; AVX512-LABEL: select_fcmp_oge_f64: 179; AVX512: # %bb.0: 180; AVX512-NEXT: vcmplesd %xmm0, %xmm1, %k1 181; AVX512-NEXT: vmovsd %xmm2, %xmm3, %xmm3 {%k1} 182; AVX512-NEXT: vmovapd %xmm3, %xmm0 183; AVX512-NEXT: retq 184 %1 = fcmp oge double %a, %b 185 %2 = select i1 %1, double %c, double %d 186 ret double %2 187} 188 189define float @select_fcmp_olt_f32(float %a, float %b, float %c, float %d) { 190; SSE-LABEL: select_fcmp_olt_f32: 191; SSE: # %bb.0: 192; SSE-NEXT: cmpltss %xmm1, %xmm0 193; SSE-NEXT: movaps %xmm0, %xmm1 194; SSE-NEXT: andps %xmm2, %xmm1 195; SSE-NEXT: andnps %xmm3, %xmm0 196; SSE-NEXT: orps %xmm1, %xmm0 197; SSE-NEXT: retq 198; 199; AVX-LABEL: select_fcmp_olt_f32: 200; AVX: # %bb.0: 201; AVX-NEXT: vcmpltss %xmm1, %xmm0, %xmm0 202; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 203; AVX-NEXT: retq 204; 205; AVX512-LABEL: select_fcmp_olt_f32: 206; AVX512: # %bb.0: 207; AVX512-NEXT: vcmpltss %xmm1, %xmm0, %k1 208; AVX512-NEXT: vmovss %xmm2, %xmm3, %xmm3 {%k1} 209; AVX512-NEXT: vmovaps %xmm3, %xmm0 210; AVX512-NEXT: retq 211 %1 = fcmp olt float %a, %b 212 %2 = select i1 %1, float %c, float %d 213 ret float %2 214} 215 216define double @select_fcmp_olt_f64(double %a, double %b, double %c, double %d) { 217; SSE-LABEL: select_fcmp_olt_f64: 218; SSE: # %bb.0: 219; SSE-NEXT: cmpltsd %xmm1, %xmm0 220; SSE-NEXT: movaps %xmm0, %xmm1 221; SSE-NEXT: andpd %xmm2, %xmm1 222; SSE-NEXT: andnpd %xmm3, %xmm0 223; SSE-NEXT: orpd %xmm1, %xmm0 224; SSE-NEXT: retq 225; 226; AVX-LABEL: select_fcmp_olt_f64: 227; AVX: # %bb.0: 228; AVX-NEXT: vcmpltsd %xmm1, %xmm0, %xmm0 229; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0 230; AVX-NEXT: retq 231; 232; AVX512-LABEL: select_fcmp_olt_f64: 233; AVX512: # %bb.0: 234; AVX512-NEXT: vcmpltsd %xmm1, %xmm0, %k1 235; AVX512-NEXT: vmovsd %xmm2, %xmm3, %xmm3 {%k1} 236; AVX512-NEXT: vmovapd %xmm3, %xmm0 237; AVX512-NEXT: retq 238 %1 = fcmp olt double %a, %b 239 %2 = select i1 %1, double %c, double %d 240 ret double %2 241} 242 243define float @select_fcmp_ole_f32(float %a, float %b, float %c, float %d) { 244; SSE-LABEL: select_fcmp_ole_f32: 245; SSE: # %bb.0: 246; SSE-NEXT: cmpless %xmm1, %xmm0 247; SSE-NEXT: movaps %xmm0, %xmm1 248; SSE-NEXT: andps %xmm2, %xmm1 249; SSE-NEXT: andnps %xmm3, %xmm0 250; SSE-NEXT: orps %xmm1, %xmm0 251; SSE-NEXT: retq 252; 253; AVX-LABEL: select_fcmp_ole_f32: 254; AVX: # %bb.0: 255; AVX-NEXT: vcmpless %xmm1, %xmm0, %xmm0 256; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 257; AVX-NEXT: retq 258; 259; AVX512-LABEL: select_fcmp_ole_f32: 260; AVX512: # %bb.0: 261; AVX512-NEXT: vcmpless %xmm1, %xmm0, %k1 262; AVX512-NEXT: vmovss %xmm2, %xmm3, %xmm3 {%k1} 263; AVX512-NEXT: vmovaps %xmm3, %xmm0 264; AVX512-NEXT: retq 265 %1 = fcmp ole float %a, %b 266 %2 = select i1 %1, float %c, float %d 267 ret float %2 268} 269 270define double @select_fcmp_ole_f64(double %a, double %b, double %c, double %d) { 271; SSE-LABEL: select_fcmp_ole_f64: 272; SSE: # %bb.0: 273; SSE-NEXT: cmplesd %xmm1, %xmm0 274; SSE-NEXT: movaps %xmm0, %xmm1 275; SSE-NEXT: andpd %xmm2, %xmm1 276; SSE-NEXT: andnpd %xmm3, %xmm0 277; SSE-NEXT: orpd %xmm1, %xmm0 278; SSE-NEXT: retq 279; 280; AVX-LABEL: select_fcmp_ole_f64: 281; AVX: # %bb.0: 282; AVX-NEXT: vcmplesd %xmm1, %xmm0, %xmm0 283; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0 284; AVX-NEXT: retq 285; 286; AVX512-LABEL: select_fcmp_ole_f64: 287; AVX512: # %bb.0: 288; AVX512-NEXT: vcmplesd %xmm1, %xmm0, %k1 289; AVX512-NEXT: vmovsd %xmm2, %xmm3, %xmm3 {%k1} 290; AVX512-NEXT: vmovapd %xmm3, %xmm0 291; AVX512-NEXT: retq 292 %1 = fcmp ole double %a, %b 293 %2 = select i1 %1, double %c, double %d 294 ret double %2 295} 296 297define float @select_fcmp_ord_f32(float %a, float %b, float %c, float %d) { 298; SSE-LABEL: select_fcmp_ord_f32: 299; SSE: # %bb.0: 300; SSE-NEXT: cmpordss %xmm1, %xmm0 301; SSE-NEXT: movaps %xmm0, %xmm1 302; SSE-NEXT: andps %xmm2, %xmm1 303; SSE-NEXT: andnps %xmm3, %xmm0 304; SSE-NEXT: orps %xmm1, %xmm0 305; SSE-NEXT: retq 306; 307; AVX-LABEL: select_fcmp_ord_f32: 308; AVX: # %bb.0: 309; AVX-NEXT: vcmpordss %xmm1, %xmm0, %xmm0 310; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 311; AVX-NEXT: retq 312; 313; AVX512-LABEL: select_fcmp_ord_f32: 314; AVX512: # %bb.0: 315; AVX512-NEXT: vcmpordss %xmm1, %xmm0, %k1 316; AVX512-NEXT: vmovss %xmm2, %xmm3, %xmm3 {%k1} 317; AVX512-NEXT: vmovaps %xmm3, %xmm0 318; AVX512-NEXT: retq 319 %1 = fcmp ord float %a, %b 320 %2 = select i1 %1, float %c, float %d 321 ret float %2 322} 323 324define double @select_fcmp_ord_f64(double %a, double %b, double %c, double %d) { 325; SSE-LABEL: select_fcmp_ord_f64: 326; SSE: # %bb.0: 327; SSE-NEXT: cmpordsd %xmm1, %xmm0 328; SSE-NEXT: movaps %xmm0, %xmm1 329; SSE-NEXT: andpd %xmm2, %xmm1 330; SSE-NEXT: andnpd %xmm3, %xmm0 331; SSE-NEXT: orpd %xmm1, %xmm0 332; SSE-NEXT: retq 333; 334; AVX-LABEL: select_fcmp_ord_f64: 335; AVX: # %bb.0: 336; AVX-NEXT: vcmpordsd %xmm1, %xmm0, %xmm0 337; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0 338; AVX-NEXT: retq 339; 340; AVX512-LABEL: select_fcmp_ord_f64: 341; AVX512: # %bb.0: 342; AVX512-NEXT: vcmpordsd %xmm1, %xmm0, %k1 343; AVX512-NEXT: vmovsd %xmm2, %xmm3, %xmm3 {%k1} 344; AVX512-NEXT: vmovapd %xmm3, %xmm0 345; AVX512-NEXT: retq 346 %1 = fcmp ord double %a, %b 347 %2 = select i1 %1, double %c, double %d 348 ret double %2 349} 350 351define float @select_fcmp_uno_f32(float %a, float %b, float %c, float %d) { 352; SSE-LABEL: select_fcmp_uno_f32: 353; SSE: # %bb.0: 354; SSE-NEXT: cmpunordss %xmm1, %xmm0 355; SSE-NEXT: movaps %xmm0, %xmm1 356; SSE-NEXT: andps %xmm2, %xmm1 357; SSE-NEXT: andnps %xmm3, %xmm0 358; SSE-NEXT: orps %xmm1, %xmm0 359; SSE-NEXT: retq 360; 361; AVX-LABEL: select_fcmp_uno_f32: 362; AVX: # %bb.0: 363; AVX-NEXT: vcmpunordss %xmm1, %xmm0, %xmm0 364; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 365; AVX-NEXT: retq 366; 367; AVX512-LABEL: select_fcmp_uno_f32: 368; AVX512: # %bb.0: 369; AVX512-NEXT: vcmpunordss %xmm1, %xmm0, %k1 370; AVX512-NEXT: vmovss %xmm2, %xmm3, %xmm3 {%k1} 371; AVX512-NEXT: vmovaps %xmm3, %xmm0 372; AVX512-NEXT: retq 373 %1 = fcmp uno float %a, %b 374 %2 = select i1 %1, float %c, float %d 375 ret float %2 376} 377 378define double @select_fcmp_uno_f64(double %a, double %b, double %c, double %d) { 379; SSE-LABEL: select_fcmp_uno_f64: 380; SSE: # %bb.0: 381; SSE-NEXT: cmpunordsd %xmm1, %xmm0 382; SSE-NEXT: movaps %xmm0, %xmm1 383; SSE-NEXT: andpd %xmm2, %xmm1 384; SSE-NEXT: andnpd %xmm3, %xmm0 385; SSE-NEXT: orpd %xmm1, %xmm0 386; SSE-NEXT: retq 387; 388; AVX-LABEL: select_fcmp_uno_f64: 389; AVX: # %bb.0: 390; AVX-NEXT: vcmpunordsd %xmm1, %xmm0, %xmm0 391; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0 392; AVX-NEXT: retq 393; 394; AVX512-LABEL: select_fcmp_uno_f64: 395; AVX512: # %bb.0: 396; AVX512-NEXT: vcmpunordsd %xmm1, %xmm0, %k1 397; AVX512-NEXT: vmovsd %xmm2, %xmm3, %xmm3 {%k1} 398; AVX512-NEXT: vmovapd %xmm3, %xmm0 399; AVX512-NEXT: retq 400 %1 = fcmp uno double %a, %b 401 %2 = select i1 %1, double %c, double %d 402 ret double %2 403} 404 405define float @select_fcmp_ugt_f32(float %a, float %b, float %c, float %d) { 406; SSE-LABEL: select_fcmp_ugt_f32: 407; SSE: # %bb.0: 408; SSE-NEXT: cmpnless %xmm1, %xmm0 409; SSE-NEXT: movaps %xmm0, %xmm1 410; SSE-NEXT: andps %xmm2, %xmm1 411; SSE-NEXT: andnps %xmm3, %xmm0 412; SSE-NEXT: orps %xmm1, %xmm0 413; SSE-NEXT: retq 414; 415; AVX-LABEL: select_fcmp_ugt_f32: 416; AVX: # %bb.0: 417; AVX-NEXT: vcmpnless %xmm1, %xmm0, %xmm0 418; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 419; AVX-NEXT: retq 420; 421; AVX512-LABEL: select_fcmp_ugt_f32: 422; AVX512: # %bb.0: 423; AVX512-NEXT: vcmpnless %xmm1, %xmm0, %k1 424; AVX512-NEXT: vmovss %xmm2, %xmm3, %xmm3 {%k1} 425; AVX512-NEXT: vmovaps %xmm3, %xmm0 426; AVX512-NEXT: retq 427 %1 = fcmp ugt float %a, %b 428 %2 = select i1 %1, float %c, float %d 429 ret float %2 430} 431 432define double @select_fcmp_ugt_f64(double %a, double %b, double %c, double %d) { 433; SSE-LABEL: select_fcmp_ugt_f64: 434; SSE: # %bb.0: 435; SSE-NEXT: cmpnlesd %xmm1, %xmm0 436; SSE-NEXT: movaps %xmm0, %xmm1 437; SSE-NEXT: andpd %xmm2, %xmm1 438; SSE-NEXT: andnpd %xmm3, %xmm0 439; SSE-NEXT: orpd %xmm1, %xmm0 440; SSE-NEXT: retq 441; 442; AVX-LABEL: select_fcmp_ugt_f64: 443; AVX: # %bb.0: 444; AVX-NEXT: vcmpnlesd %xmm1, %xmm0, %xmm0 445; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0 446; AVX-NEXT: retq 447; 448; AVX512-LABEL: select_fcmp_ugt_f64: 449; AVX512: # %bb.0: 450; AVX512-NEXT: vcmpnlesd %xmm1, %xmm0, %k1 451; AVX512-NEXT: vmovsd %xmm2, %xmm3, %xmm3 {%k1} 452; AVX512-NEXT: vmovapd %xmm3, %xmm0 453; AVX512-NEXT: retq 454 %1 = fcmp ugt double %a, %b 455 %2 = select i1 %1, double %c, double %d 456 ret double %2 457} 458 459define float @select_fcmp_uge_f32(float %a, float %b, float %c, float %d) { 460; SSE-LABEL: select_fcmp_uge_f32: 461; SSE: # %bb.0: 462; SSE-NEXT: cmpnltss %xmm1, %xmm0 463; SSE-NEXT: movaps %xmm0, %xmm1 464; SSE-NEXT: andps %xmm2, %xmm1 465; SSE-NEXT: andnps %xmm3, %xmm0 466; SSE-NEXT: orps %xmm1, %xmm0 467; SSE-NEXT: retq 468; 469; AVX-LABEL: select_fcmp_uge_f32: 470; AVX: # %bb.0: 471; AVX-NEXT: vcmpnltss %xmm1, %xmm0, %xmm0 472; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 473; AVX-NEXT: retq 474; 475; AVX512-LABEL: select_fcmp_uge_f32: 476; AVX512: # %bb.0: 477; AVX512-NEXT: vcmpnltss %xmm1, %xmm0, %k1 478; AVX512-NEXT: vmovss %xmm2, %xmm3, %xmm3 {%k1} 479; AVX512-NEXT: vmovaps %xmm3, %xmm0 480; AVX512-NEXT: retq 481 %1 = fcmp uge float %a, %b 482 %2 = select i1 %1, float %c, float %d 483 ret float %2 484} 485 486define double @select_fcmp_uge_f64(double %a, double %b, double %c, double %d) { 487; SSE-LABEL: select_fcmp_uge_f64: 488; SSE: # %bb.0: 489; SSE-NEXT: cmpnltsd %xmm1, %xmm0 490; SSE-NEXT: movaps %xmm0, %xmm1 491; SSE-NEXT: andpd %xmm2, %xmm1 492; SSE-NEXT: andnpd %xmm3, %xmm0 493; SSE-NEXT: orpd %xmm1, %xmm0 494; SSE-NEXT: retq 495; 496; AVX-LABEL: select_fcmp_uge_f64: 497; AVX: # %bb.0: 498; AVX-NEXT: vcmpnltsd %xmm1, %xmm0, %xmm0 499; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0 500; AVX-NEXT: retq 501; 502; AVX512-LABEL: select_fcmp_uge_f64: 503; AVX512: # %bb.0: 504; AVX512-NEXT: vcmpnltsd %xmm1, %xmm0, %k1 505; AVX512-NEXT: vmovsd %xmm2, %xmm3, %xmm3 {%k1} 506; AVX512-NEXT: vmovapd %xmm3, %xmm0 507; AVX512-NEXT: retq 508 %1 = fcmp uge double %a, %b 509 %2 = select i1 %1, double %c, double %d 510 ret double %2 511} 512 513define float @select_fcmp_ult_f32(float %a, float %b, float %c, float %d) { 514; SSE-LABEL: select_fcmp_ult_f32: 515; SSE: # %bb.0: 516; SSE-NEXT: movss %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill 517; SSE-NEXT: movaps %xmm0, %xmm1 518; SSE-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload 519; SSE-NEXT: # xmm0 = mem[0],zero,zero,zero 520; SSE-NEXT: cmpnless %xmm1, %xmm0 521; SSE-NEXT: movaps %xmm0, %xmm1 522; SSE-NEXT: andps %xmm2, %xmm1 523; SSE-NEXT: andnps %xmm3, %xmm0 524; SSE-NEXT: orps %xmm1, %xmm0 525; SSE-NEXT: retq 526; 527; AVX-LABEL: select_fcmp_ult_f32: 528; AVX: # %bb.0: 529; AVX-NEXT: vcmpnless %xmm0, %xmm1, %xmm0 530; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 531; AVX-NEXT: retq 532; 533; AVX512-LABEL: select_fcmp_ult_f32: 534; AVX512: # %bb.0: 535; AVX512-NEXT: vcmpnless %xmm0, %xmm1, %k1 536; AVX512-NEXT: vmovss %xmm2, %xmm3, %xmm3 {%k1} 537; AVX512-NEXT: vmovaps %xmm3, %xmm0 538; AVX512-NEXT: retq 539 %1 = fcmp ult float %a, %b 540 %2 = select i1 %1, float %c, float %d 541 ret float %2 542} 543 544define double @select_fcmp_ult_f64(double %a, double %b, double %c, double %d) { 545; SSE-LABEL: select_fcmp_ult_f64: 546; SSE: # %bb.0: 547; SSE-NEXT: movsd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill 548; SSE-NEXT: movaps %xmm0, %xmm1 549; SSE-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload 550; SSE-NEXT: # xmm0 = mem[0],zero 551; SSE-NEXT: cmpnlesd %xmm1, %xmm0 552; SSE-NEXT: movaps %xmm0, %xmm1 553; SSE-NEXT: andpd %xmm2, %xmm1 554; SSE-NEXT: andnpd %xmm3, %xmm0 555; SSE-NEXT: orpd %xmm1, %xmm0 556; SSE-NEXT: retq 557; 558; AVX-LABEL: select_fcmp_ult_f64: 559; AVX: # %bb.0: 560; AVX-NEXT: vcmpnlesd %xmm0, %xmm1, %xmm0 561; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0 562; AVX-NEXT: retq 563; 564; AVX512-LABEL: select_fcmp_ult_f64: 565; AVX512: # %bb.0: 566; AVX512-NEXT: vcmpnlesd %xmm0, %xmm1, %k1 567; AVX512-NEXT: vmovsd %xmm2, %xmm3, %xmm3 {%k1} 568; AVX512-NEXT: vmovapd %xmm3, %xmm0 569; AVX512-NEXT: retq 570 %1 = fcmp ult double %a, %b 571 %2 = select i1 %1, double %c, double %d 572 ret double %2 573} 574 575define float @select_fcmp_ule_f32(float %a, float %b, float %c, float %d) { 576; SSE-LABEL: select_fcmp_ule_f32: 577; SSE: # %bb.0: 578; SSE-NEXT: movss %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill 579; SSE-NEXT: movaps %xmm0, %xmm1 580; SSE-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload 581; SSE-NEXT: # xmm0 = mem[0],zero,zero,zero 582; SSE-NEXT: cmpnltss %xmm1, %xmm0 583; SSE-NEXT: movaps %xmm0, %xmm1 584; SSE-NEXT: andps %xmm2, %xmm1 585; SSE-NEXT: andnps %xmm3, %xmm0 586; SSE-NEXT: orps %xmm1, %xmm0 587; SSE-NEXT: retq 588; 589; AVX-LABEL: select_fcmp_ule_f32: 590; AVX: # %bb.0: 591; AVX-NEXT: vcmpnltss %xmm0, %xmm1, %xmm0 592; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 593; AVX-NEXT: retq 594; 595; AVX512-LABEL: select_fcmp_ule_f32: 596; AVX512: # %bb.0: 597; AVX512-NEXT: vcmpnltss %xmm0, %xmm1, %k1 598; AVX512-NEXT: vmovss %xmm2, %xmm3, %xmm3 {%k1} 599; AVX512-NEXT: vmovaps %xmm3, %xmm0 600; AVX512-NEXT: retq 601 %1 = fcmp ule float %a, %b 602 %2 = select i1 %1, float %c, float %d 603 ret float %2 604} 605 606define double @select_fcmp_ule_f64(double %a, double %b, double %c, double %d) { 607; SSE-LABEL: select_fcmp_ule_f64: 608; SSE: # %bb.0: 609; SSE-NEXT: movsd %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill 610; SSE-NEXT: movaps %xmm0, %xmm1 611; SSE-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload 612; SSE-NEXT: # xmm0 = mem[0],zero 613; SSE-NEXT: cmpnltsd %xmm1, %xmm0 614; SSE-NEXT: movaps %xmm0, %xmm1 615; SSE-NEXT: andpd %xmm2, %xmm1 616; SSE-NEXT: andnpd %xmm3, %xmm0 617; SSE-NEXT: orpd %xmm1, %xmm0 618; SSE-NEXT: retq 619; 620; AVX-LABEL: select_fcmp_ule_f64: 621; AVX: # %bb.0: 622; AVX-NEXT: vcmpnltsd %xmm0, %xmm1, %xmm0 623; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0 624; AVX-NEXT: retq 625; 626; AVX512-LABEL: select_fcmp_ule_f64: 627; AVX512: # %bb.0: 628; AVX512-NEXT: vcmpnltsd %xmm0, %xmm1, %k1 629; AVX512-NEXT: vmovsd %xmm2, %xmm3, %xmm3 {%k1} 630; AVX512-NEXT: vmovapd %xmm3, %xmm0 631; AVX512-NEXT: retq 632 %1 = fcmp ule double %a, %b 633 %2 = select i1 %1, double %c, double %d 634 ret double %2 635} 636 637define float @select_fcmp_une_f32(float %a, float %b, float %c, float %d) { 638; SSE-LABEL: select_fcmp_une_f32: 639; SSE: # %bb.0: 640; SSE-NEXT: cmpneqss %xmm1, %xmm0 641; SSE-NEXT: movaps %xmm0, %xmm1 642; SSE-NEXT: andps %xmm2, %xmm1 643; SSE-NEXT: andnps %xmm3, %xmm0 644; SSE-NEXT: orps %xmm1, %xmm0 645; SSE-NEXT: retq 646; 647; AVX-LABEL: select_fcmp_une_f32: 648; AVX: # %bb.0: 649; AVX-NEXT: vcmpneqss %xmm1, %xmm0, %xmm0 650; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 651; AVX-NEXT: retq 652; 653; AVX512-LABEL: select_fcmp_une_f32: 654; AVX512: # %bb.0: 655; AVX512-NEXT: vcmpneqss %xmm1, %xmm0, %k1 656; AVX512-NEXT: vmovss %xmm2, %xmm3, %xmm3 {%k1} 657; AVX512-NEXT: vmovaps %xmm3, %xmm0 658; AVX512-NEXT: retq 659 %1 = fcmp une float %a, %b 660 %2 = select i1 %1, float %c, float %d 661 ret float %2 662} 663 664define double @select_fcmp_une_f64(double %a, double %b, double %c, double %d) { 665; SSE-LABEL: select_fcmp_une_f64: 666; SSE: # %bb.0: 667; SSE-NEXT: cmpneqsd %xmm1, %xmm0 668; SSE-NEXT: movaps %xmm0, %xmm1 669; SSE-NEXT: andpd %xmm2, %xmm1 670; SSE-NEXT: andnpd %xmm3, %xmm0 671; SSE-NEXT: orpd %xmm1, %xmm0 672; SSE-NEXT: retq 673; 674; AVX-LABEL: select_fcmp_une_f64: 675; AVX: # %bb.0: 676; AVX-NEXT: vcmpneqsd %xmm1, %xmm0, %xmm0 677; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0 678; AVX-NEXT: retq 679; 680; AVX512-LABEL: select_fcmp_une_f64: 681; AVX512: # %bb.0: 682; AVX512-NEXT: vcmpneqsd %xmm1, %xmm0, %k1 683; AVX512-NEXT: vmovsd %xmm2, %xmm3, %xmm3 {%k1} 684; AVX512-NEXT: vmovapd %xmm3, %xmm0 685; AVX512-NEXT: retq 686 %1 = fcmp une double %a, %b 687 %2 = select i1 %1, double %c, double %d 688 ret double %2 689} 690 691