1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X86,X86_AVX256 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X64,X64_AVX256 4; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X86,X86_AVX512 5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X64,X64_AVX512 6 7define <8 x float> @insert_subvector_256(i16 %x0, i16 %x1, <8 x float> %v) nounwind { 8; X86-LABEL: insert_subvector_256: 9; X86: # %bb.0: 10; X86-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero 11; X86-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1 12; X86-NEXT: vpbroadcastd %xmm1, %xmm1 13; X86-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7] 14; X86-NEXT: retl 15; 16; X64-LABEL: insert_subvector_256: 17; X64: # %bb.0: 18; X64-NEXT: vmovd %edi, %xmm1 19; X64-NEXT: vpinsrw $1, %esi, %xmm1, %xmm1 20; X64-NEXT: vpbroadcastd %xmm1, %xmm1 21; X64-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7] 22; X64-NEXT: retq 23 %ins1 = insertelement <2 x i16> undef, i16 %x0, i32 0 24 %ins2 = insertelement <2 x i16> %ins1, i16 %x1, i32 1 25 %bc = bitcast <2 x i16> %ins2 to float 26 %ins3 = insertelement <8 x float> %v, float %bc, i32 1 27 ret <8 x float> %ins3 28} 29 30define <8 x i64> @insert_subvector_512(i32 %x0, i32 %x1, <8 x i64> %v) nounwind { 31; X86_AVX256-LABEL: insert_subvector_512: 32; X86_AVX256: # %bb.0: 33; X86_AVX256-NEXT: vextracti128 $1, %ymm0, %xmm2 34; X86_AVX256-NEXT: vpinsrd $0, {{[0-9]+}}(%esp), %xmm2, %xmm2 35; X86_AVX256-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm2, %xmm2 36; X86_AVX256-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0 37; X86_AVX256-NEXT: retl 38; 39; X64_AVX256-LABEL: insert_subvector_512: 40; X64_AVX256: # %bb.0: 41; X64_AVX256-NEXT: vmovd %edi, %xmm2 42; X64_AVX256-NEXT: vpinsrd $1, %esi, %xmm2, %xmm2 43; X64_AVX256-NEXT: vextracti128 $1, %ymm0, %xmm3 44; X64_AVX256-NEXT: vpblendd {{.*#+}} xmm2 = xmm2[0,1],xmm3[2,3] 45; X64_AVX256-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0 46; X64_AVX256-NEXT: retq 47; 48; X86_AVX512-LABEL: insert_subvector_512: 49; X86_AVX512: # %bb.0: 50; X86_AVX512-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero 51; X86_AVX512-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,0,1,0,8,0,3,0,4,0,5,0,6,0,7,0] 52; X86_AVX512-NEXT: vpermt2q %zmm1, %zmm2, %zmm0 53; X86_AVX512-NEXT: retl 54; 55; X64_AVX512-LABEL: insert_subvector_512: 56; X64_AVX512: # %bb.0: 57; X64_AVX512-NEXT: vmovd %edi, %xmm1 58; X64_AVX512-NEXT: vpinsrd $1, %esi, %xmm1, %xmm1 59; X64_AVX512-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,8,3,4,5,6,7] 60; X64_AVX512-NEXT: vpermt2q %zmm1, %zmm2, %zmm0 61; X64_AVX512-NEXT: retq 62 %ins1 = insertelement <2 x i32> undef, i32 %x0, i32 0 63 %ins2 = insertelement <2 x i32> %ins1, i32 %x1, i32 1 64 %bc = bitcast <2 x i32> %ins2 to i64 65 %ins3 = insertelement <8 x i64> %v, i64 %bc, i32 2 66 ret <8 x i64> %ins3 67} 68 69; PR34716 - https://bugs.llvm.org/show_bug.cgi?id=34716 70; Special case: if we're inserting into an undef vector, we can optimize more. 71 72define <8 x i64> @insert_subvector_into_undef(i32 %x0, i32 %x1) nounwind { 73; X86_AVX256-LABEL: insert_subvector_into_undef: 74; X86_AVX256: # %bb.0: 75; X86_AVX256-NEXT: vbroadcastsd {{[0-9]+}}(%esp), %ymm0 76; X86_AVX256-NEXT: vmovaps %ymm0, %ymm1 77; X86_AVX256-NEXT: retl 78; 79; X64_AVX256-LABEL: insert_subvector_into_undef: 80; X64_AVX256: # %bb.0: 81; X64_AVX256-NEXT: vmovd %edi, %xmm0 82; X64_AVX256-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0 83; X64_AVX256-NEXT: vpbroadcastq %xmm0, %ymm0 84; X64_AVX256-NEXT: vmovdqa %ymm0, %ymm1 85; X64_AVX256-NEXT: retq 86; 87; X86_AVX512-LABEL: insert_subvector_into_undef: 88; X86_AVX512: # %bb.0: 89; X86_AVX512-NEXT: vbroadcastsd {{[0-9]+}}(%esp), %zmm0 90; X86_AVX512-NEXT: retl 91; 92; X64_AVX512-LABEL: insert_subvector_into_undef: 93; X64_AVX512: # %bb.0: 94; X64_AVX512-NEXT: vmovd %edi, %xmm0 95; X64_AVX512-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0 96; X64_AVX512-NEXT: vpbroadcastq %xmm0, %zmm0 97; X64_AVX512-NEXT: retq 98 %ins1 = insertelement <2 x i32> undef, i32 %x0, i32 0 99 %ins2 = insertelement <2 x i32> %ins1, i32 %x1, i32 1 100 %bc = bitcast <2 x i32> %ins2 to i64 101 %ins3 = insertelement <8 x i64> undef, i64 %bc, i32 0 102 %splat = shufflevector <8 x i64> %ins3, <8 x i64> undef, <8 x i32> zeroinitializer 103 ret <8 x i64> %splat 104} 105 106