1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-- -mattr=avx512vl | FileCheck %s 3 4define <2 x i64> @undef_tval() { 5; CHECK-LABEL: undef_tval: 6; CHECK: # %bb.0: 7; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [1,1,1,1,1,1,1,1] 8; CHECK-NEXT: movb $1, %al 9; CHECK-NEXT: kmovw %eax, %k1 10; CHECK-NEXT: vpmovqw %zmm0, %xmm0 {%k1} 11; CHECK-NEXT: vzeroupper 12; CHECK-NEXT: retq 13 %1 = tail call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> undef, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, i8 1) #3 14 %2 = bitcast <8 x i16> %1 to <2 x i64> 15 ret <2 x i64> %2 16} 17 18define <2 x i64> @foo(<8 x i64> %x) { 19; CHECK-LABEL: foo: 20; CHECK: # %bb.0: 21; CHECK-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,1,1,1,1,1] 22; CHECK-NEXT: movb $1, %al 23; CHECK-NEXT: kmovw %eax, %k1 24; CHECK-NEXT: vpmovqw %zmm0, %xmm1 {%k1} 25; CHECK-NEXT: vmovdqa %xmm1, %xmm0 26; CHECK-NEXT: vzeroupper 27; CHECK-NEXT: retq 28 %1 = tail call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %x, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, i8 1) #3 29 %2 = bitcast <8 x i16> %1 to <2 x i64> 30 ret <2 x i64> %2 31} 32 33define <4 x i64> @goo(<16 x i32> %x) { 34; CHECK-LABEL: goo: 35; CHECK: # %bb.0: 36; CHECK-NEXT: vmovdqa {{.*#+}} ymm1 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] 37; CHECK-NEXT: movw $1, %ax 38; CHECK-NEXT: kmovw %eax, %k1 39; CHECK-NEXT: vpmovdw %zmm0, %ymm1 {%k1} 40; CHECK-NEXT: vmovdqa %ymm1, %ymm0 41; CHECK-NEXT: retq 42 %1 = tail call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> %x, <16 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, i16 1) #3 43 %2 = bitcast <16 x i16> %1 to <4 x i64> 44 ret <4 x i64> %2 45} 46 47 48declare <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64>, <8 x i16>, i8) 49declare <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32>, <16 x i16>, i16) 50