1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s 3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx512f | FileCheck %s 4 5; This test makes sure that a vector that needs to be promoted that is bitcasted to fp16 is legalized correctly without causing a width mismatch. 6define void @constant_fold_vector_to_half() { 7; CHECK-LABEL: constant_fold_vector_to_half: 8; CHECK: # %bb.0: 9; CHECK-NEXT: movw $16384, (%rax) # imm = 0x4000 10; CHECK-NEXT: retq 11 store volatile half bitcast (<4 x i4> <i4 0, i4 0, i4 0, i4 4> to half), half* undef 12 ret void 13} 14 15; Similarly this makes sure that the opposite bitcast of the above is also legalized without crashing. 16define void @pr38533_2(half %x) { 17; CHECK-LABEL: pr38533_2: 18; CHECK: # %bb.0: 19; CHECK-NEXT: movw %di, (%rax) 20; CHECK-NEXT: retq 21 %a = bitcast half %x to <4 x i4> 22 store volatile <4 x i4> %a, <4 x i4>* undef 23 ret void 24} 25 26; This case is a bitcast from fp16 to a 16-bit wide legal vector type. In this case the result type is legal when the bitcast gets type legalized. 27define void @pr38533_3(half %x) { 28; CHECK-LABEL: pr38533_3: 29; CHECK: # %bb.0: 30; CHECK-NEXT: movw %di, (%rax) 31; CHECK-NEXT: retq 32 %a = bitcast half %x to <16 x i1> 33 store volatile <16 x i1> %a, <16 x i1>* undef 34 ret void 35} 36