1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-linux -mcpu=x86-64 | FileCheck %s 3 4define x86_fp80 @rem_pio2l_min(x86_fp80 %z) { 5; CHECK-LABEL: rem_pio2l_min: 6; CHECK: # %bb.0: # %entry 7; CHECK-NEXT: fldt {{[0-9]+}}(%rsp) 8; CHECK-NEXT: fnstcw -{{[0-9]+}}(%rsp) 9; CHECK-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax 10; CHECK-NEXT: orl $3072, %eax # imm = 0xC00 11; CHECK-NEXT: movw %ax, -{{[0-9]+}}(%rsp) 12; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp) 13; CHECK-NEXT: fistl -{{[0-9]+}}(%rsp) 14; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp) 15; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax 16; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp) 17; CHECK-NEXT: fisubl -{{[0-9]+}}(%rsp) 18; CHECK-NEXT: flds {{.*}}(%rip) 19; CHECK-NEXT: fmul %st, %st(1) 20; CHECK-NEXT: fnstcw -{{[0-9]+}}(%rsp) 21; CHECK-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax 22; CHECK-NEXT: orl $3072, %eax # imm = 0xC00 23; CHECK-NEXT: movw %ax, -{{[0-9]+}}(%rsp) 24; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp) 25; CHECK-NEXT: fxch %st(1) 26; CHECK-NEXT: fistl -{{[0-9]+}}(%rsp) 27; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp) 28; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax 29; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp) 30; CHECK-NEXT: fisubl -{{[0-9]+}}(%rsp) 31; CHECK-NEXT: fmulp %st, %st(1) 32; CHECK-NEXT: retq 33entry: 34 %conv = fptosi x86_fp80 %z to i32 35 %conv1 = sitofp i32 %conv to x86_fp80 36 %sub = fsub x86_fp80 %z, %conv1 37 %mul = fmul x86_fp80 %sub, 0xK40178000000000000000 38 %conv2 = fptosi x86_fp80 %mul to i32 39 %conv3 = sitofp i32 %conv2 to x86_fp80 40 %sub4 = fsub x86_fp80 %mul, %conv3 41 %mul5 = fmul x86_fp80 %sub4, 0xK40178000000000000000 42 ret x86_fp80 %mul5 43} 44