1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,SSE 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX1 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX2 5 6define i32 @shl48sar47(i64 %a) #0 { 7; CHECK-LABEL: shl48sar47: 8; CHECK: # %bb.0: 9; CHECK-NEXT: movswq %di, %rax 10; CHECK-NEXT: addl %eax, %eax 11; CHECK-NEXT: # kill: def $eax killed $eax killed $rax 12; CHECK-NEXT: retq 13 %1 = shl i64 %a, 48 14 %2 = ashr exact i64 %1, 47 15 %3 = trunc i64 %2 to i32 16 ret i32 %3 17} 18 19define i32 @shl48sar49(i64 %a) #0 { 20; CHECK-LABEL: shl48sar49: 21; CHECK: # %bb.0: 22; CHECK-NEXT: movswq %di, %rax 23; CHECK-NEXT: shrq %rax 24; CHECK-NEXT: # kill: def $eax killed $eax killed $rax 25; CHECK-NEXT: retq 26 %1 = shl i64 %a, 48 27 %2 = ashr exact i64 %1, 49 28 %3 = trunc i64 %2 to i32 29 ret i32 %3 30} 31 32define i32 @shl56sar55(i64 %a) #0 { 33; CHECK-LABEL: shl56sar55: 34; CHECK: # %bb.0: 35; CHECK-NEXT: movsbq %dil, %rax 36; CHECK-NEXT: addl %eax, %eax 37; CHECK-NEXT: # kill: def $eax killed $eax killed $rax 38; CHECK-NEXT: retq 39 %1 = shl i64 %a, 56 40 %2 = ashr exact i64 %1, 55 41 %3 = trunc i64 %2 to i32 42 ret i32 %3 43} 44 45define i32 @shl56sar57(i64 %a) #0 { 46; CHECK-LABEL: shl56sar57: 47; CHECK: # %bb.0: 48; CHECK-NEXT: movsbq %dil, %rax 49; CHECK-NEXT: shrq %rax 50; CHECK-NEXT: # kill: def $eax killed $eax killed $rax 51; CHECK-NEXT: retq 52 %1 = shl i64 %a, 56 53 %2 = ashr exact i64 %1, 57 54 %3 = trunc i64 %2 to i32 55 ret i32 %3 56} 57 58define i8 @all_sign_bit_ashr(i8 %x) { 59; CHECK-LABEL: all_sign_bit_ashr: 60; CHECK: # %bb.0: 61; CHECK-NEXT: movl %edi, %eax 62; CHECK-NEXT: andb $1, %al 63; CHECK-NEXT: negb %al 64; CHECK-NEXT: # kill: def $al killed $al killed $eax 65; CHECK-NEXT: retq 66 %and = and i8 %x, 1 67 %neg = sub i8 0, %and 68 %sar = ashr i8 %neg, 6 69 ret i8 %sar 70} 71 72define <4 x i32> @all_sign_bit_ashr_vec0(<4 x i32> %x) { 73; SSE-LABEL: all_sign_bit_ashr_vec0: 74; SSE: # %bb.0: 75; SSE-NEXT: pand {{.*}}(%rip), %xmm0 76; SSE-NEXT: pxor %xmm1, %xmm1 77; SSE-NEXT: psubd %xmm0, %xmm1 78; SSE-NEXT: movdqa %xmm1, %xmm0 79; SSE-NEXT: retq 80; 81; AVX1-LABEL: all_sign_bit_ashr_vec0: 82; AVX1: # %bb.0: 83; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 84; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 85; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm0 86; AVX1-NEXT: retq 87; 88; AVX2-LABEL: all_sign_bit_ashr_vec0: 89; AVX2: # %bb.0: 90; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1] 91; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 92; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 93; AVX2-NEXT: vpsubd %xmm0, %xmm1, %xmm0 94; AVX2-NEXT: retq 95 %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1> 96 %neg = sub <4 x i32> zeroinitializer, %and 97 %sar = ashr <4 x i32> %neg, <i32 1, i32 31, i32 5, i32 0> 98 ret <4 x i32> %sar 99} 100 101define <4 x i32> @all_sign_bit_ashr_vec1(<4 x i32> %x) { 102; SSE-LABEL: all_sign_bit_ashr_vec1: 103; SSE: # %bb.0: 104; SSE-NEXT: pand {{.*}}(%rip), %xmm0 105; SSE-NEXT: pxor %xmm1, %xmm1 106; SSE-NEXT: psubd %xmm0, %xmm1 107; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,0,0] 108; SSE-NEXT: retq 109; 110; AVX1-LABEL: all_sign_bit_ashr_vec1: 111; AVX1: # %bb.0: 112; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 113; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 114; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm0 115; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] 116; AVX1-NEXT: retq 117; 118; AVX2-LABEL: all_sign_bit_ashr_vec1: 119; AVX2: # %bb.0: 120; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1] 121; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 122; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 123; AVX2-NEXT: vpsubd %xmm0, %xmm1, %xmm0 124; AVX2-NEXT: vpbroadcastd %xmm0, %xmm0 125; AVX2-NEXT: retq 126 %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1> 127 %sub = sub <4 x i32> <i32 0, i32 1, i32 2, i32 3>, %and 128 %shf = shufflevector <4 x i32> %sub, <4 x i32> undef, <4 x i32> zeroinitializer 129 %sar = ashr <4 x i32> %shf, <i32 1, i32 31, i32 5, i32 0> 130 ret <4 x i32> %sar 131} 132 133define <4 x i32> @all_sign_bit_ashr_vec2(<4 x i32> %x) { 134; SSE-LABEL: all_sign_bit_ashr_vec2: 135; SSE: # %bb.0: 136; SSE-NEXT: pand {{.*}}(%rip), %xmm0 137; SSE-NEXT: pcmpeqd %xmm1, %xmm1 138; SSE-NEXT: paddd %xmm1, %xmm0 139; SSE-NEXT: retq 140; 141; AVX1-LABEL: all_sign_bit_ashr_vec2: 142; AVX1: # %bb.0: 143; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 144; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 145; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 146; AVX1-NEXT: retq 147; 148; AVX2-LABEL: all_sign_bit_ashr_vec2: 149; AVX2: # %bb.0: 150; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1] 151; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 152; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 153; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 154; AVX2-NEXT: retq 155 %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1> 156 %add = add <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> 157 %sar = ashr <4 x i32> %add, <i32 1, i32 31, i32 5, i32 0> 158 ret <4 x i32> %sar 159} 160 161define <4 x i32> @all_sign_bit_ashr_vec3(<4 x i32> %x) { 162; SSE-LABEL: all_sign_bit_ashr_vec3: 163; SSE: # %bb.0: 164; SSE-NEXT: pand {{.*}}(%rip), %xmm0 165; SSE-NEXT: pcmpeqd %xmm1, %xmm1 166; SSE-NEXT: paddd %xmm0, %xmm1 167; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,0,0] 168; SSE-NEXT: retq 169; 170; AVX1-LABEL: all_sign_bit_ashr_vec3: 171; AVX1: # %bb.0: 172; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 173; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 174; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 175; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] 176; AVX1-NEXT: retq 177; 178; AVX2-LABEL: all_sign_bit_ashr_vec3: 179; AVX2: # %bb.0: 180; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1] 181; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 182; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 183; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 184; AVX2-NEXT: vpbroadcastd %xmm0, %xmm0 185; AVX2-NEXT: retq 186 %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1> 187 %add = add <4 x i32> %and, <i32 -1, i32 1, i32 2, i32 3> 188 %shf = shufflevector <4 x i32> %add, <4 x i32> undef, <4 x i32> zeroinitializer 189 %sar = ashr <4 x i32> %shf, <i32 1, i32 31, i32 5, i32 0> 190 ret <4 x i32> %sar 191} 192 193attributes #0 = { nounwind } 194