1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefix=SSE 3; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefix=AVX 4 5; If targetShrinkDemandedConstant extends xor/or constants ensure it extends from the msb of the active bits 6define <4 x i32> @sext_vector_constants(<4 x i32> %a0) { 7; SSE-LABEL: sext_vector_constants: 8; SSE: # %bb.0: 9; SSE-NEXT: psrld $9, %xmm0 10; SSE-NEXT: pxor {{.*}}(%rip), %xmm0 11; SSE-NEXT: pslld $26, %xmm0 12; SSE-NEXT: retq 13; 14; AVX-LABEL: sext_vector_constants: 15; AVX: # %bb.0: 16; AVX-NEXT: vpsrld $9, %xmm0, %xmm0 17; AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 18; AVX-NEXT: vpslld $26, %xmm0, %xmm0 19; AVX-NEXT: retq 20 %1 = lshr <4 x i32> %a0, <i32 9, i32 9, i32 9, i32 9> 21 %2 = xor <4 x i32> %1, <i32 314523200, i32 -2085372448, i32 144496960, i32 1532773600> 22 %3 = shl <4 x i32> %2, <i32 26, i32 26, i32 26, i32 26> 23 ret <4 x i32> %3 24} 25