1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41 3; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=AVX 4; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512vl,avx512bw | FileCheck %s --check-prefix=AVX 5 6define <8 x i16> @test_llvm_x86_sse41_pmovsxbw(<16 x i8>* %a) { 7; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbw: 8; SSE41: ## %bb.0: 9; SSE41-NEXT: pmovsxbw (%rdi), %xmm0 10; SSE41-NEXT: retq 11; 12; AVX-LABEL: test_llvm_x86_sse41_pmovsxbw: 13; AVX: ## %bb.0: 14; AVX-NEXT: vpmovsxbw (%rdi), %xmm0 15; AVX-NEXT: retq 16 %1 = load <16 x i8>, <16 x i8>* %a, align 1 17 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 18 %3 = sext <8 x i8> %2 to <8 x i16> 19 ret <8 x i16> %3 20} 21 22define <4 x i32> @test_llvm_x86_sse41_pmovsxbd(<16 x i8>* %a) { 23; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbd: 24; SSE41: ## %bb.0: 25; SSE41-NEXT: pmovsxbd (%rdi), %xmm0 26; SSE41-NEXT: retq 27; 28; AVX-LABEL: test_llvm_x86_sse41_pmovsxbd: 29; AVX: ## %bb.0: 30; AVX-NEXT: vpmovsxbd (%rdi), %xmm0 31; AVX-NEXT: retq 32 %1 = load <16 x i8>, <16 x i8>* %a, align 1 33 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 34 %3 = sext <4 x i8> %2 to <4 x i32> 35 ret <4 x i32> %3 36} 37 38define <2 x i64> @test_llvm_x86_sse41_pmovsxbq(<16 x i8>* %a) { 39; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbq: 40; SSE41: ## %bb.0: 41; SSE41-NEXT: pmovsxbq (%rdi), %xmm0 42; SSE41-NEXT: retq 43; 44; AVX-LABEL: test_llvm_x86_sse41_pmovsxbq: 45; AVX: ## %bb.0: 46; AVX-NEXT: vpmovsxbq (%rdi), %xmm0 47; AVX-NEXT: retq 48 %1 = load <16 x i8>, <16 x i8>* %a, align 1 49 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <2 x i32> <i32 0, i32 1> 50 %3 = sext <2 x i8> %2 to <2 x i64> 51 ret <2 x i64> %3 52} 53 54define <4 x i32> @test_llvm_x86_sse41_pmovsxwd(<8 x i16>* %a) { 55; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwd: 56; SSE41: ## %bb.0: 57; SSE41-NEXT: pmovsxwd (%rdi), %xmm0 58; SSE41-NEXT: retq 59; 60; AVX-LABEL: test_llvm_x86_sse41_pmovsxwd: 61; AVX: ## %bb.0: 62; AVX-NEXT: vpmovsxwd (%rdi), %xmm0 63; AVX-NEXT: retq 64 %1 = load <8 x i16>, <8 x i16>* %a, align 1 65 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 66 %3 = sext <4 x i16> %2 to <4 x i32> 67 ret <4 x i32> %3 68} 69 70define <2 x i64> @test_llvm_x86_sse41_pmovsxwq(<8 x i16>* %a) { 71; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwq: 72; SSE41: ## %bb.0: 73; SSE41-NEXT: pmovsxwq (%rdi), %xmm0 74; SSE41-NEXT: retq 75; 76; AVX-LABEL: test_llvm_x86_sse41_pmovsxwq: 77; AVX: ## %bb.0: 78; AVX-NEXT: vpmovsxwq (%rdi), %xmm0 79; AVX-NEXT: retq 80 %1 = load <8 x i16>, <8 x i16>* %a, align 1 81 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <2 x i32> <i32 0, i32 1> 82 %3 = sext <2 x i16> %2 to <2 x i64> 83 ret <2 x i64> %3 84} 85 86define <2 x i64> @test_llvm_x86_sse41_pmovsxdq(<4 x i32>* %a) { 87; SSE41-LABEL: test_llvm_x86_sse41_pmovsxdq: 88; SSE41: ## %bb.0: 89; SSE41-NEXT: pmovsxdq (%rdi), %xmm0 90; SSE41-NEXT: retq 91; 92; AVX-LABEL: test_llvm_x86_sse41_pmovsxdq: 93; AVX: ## %bb.0: 94; AVX-NEXT: vpmovsxdq (%rdi), %xmm0 95; AVX-NEXT: retq 96 %1 = load <4 x i32>, <4 x i32>* %a, align 1 97 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1> 98 %3 = sext <2 x i32> %2 to <2 x i64> 99 ret <2 x i64> %3 100} 101 102define <8 x i16> @test_llvm_x86_sse41_pmovzxbw(<16 x i8>* %a) { 103; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbw: 104; SSE41: ## %bb.0: 105; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero 106; SSE41-NEXT: retq 107; 108; AVX-LABEL: test_llvm_x86_sse41_pmovzxbw: 109; AVX: ## %bb.0: 110; AVX-NEXT: vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero 111; AVX-NEXT: retq 112 %1 = load <16 x i8>, <16 x i8>* %a, align 1 113 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 114 %3 = zext <8 x i8> %2 to <8 x i16> 115 ret <8 x i16> %3 116} 117 118define <4 x i32> @test_llvm_x86_sse41_pmovzxbd(<16 x i8>* %a) { 119; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbd: 120; SSE41: ## %bb.0: 121; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero 122; SSE41-NEXT: retq 123; 124; AVX-LABEL: test_llvm_x86_sse41_pmovzxbd: 125; AVX: ## %bb.0: 126; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero 127; AVX-NEXT: retq 128 %1 = load <16 x i8>, <16 x i8>* %a, align 1 129 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 130 %3 = zext <4 x i8> %2 to <4 x i32> 131 ret <4 x i32> %3 132} 133 134define <2 x i64> @test_llvm_x86_sse41_pmovzxbq(<16 x i8>* %a) { 135; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbq: 136; SSE41: ## %bb.0: 137; SSE41-NEXT: pmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero 138; SSE41-NEXT: retq 139; 140; AVX-LABEL: test_llvm_x86_sse41_pmovzxbq: 141; AVX: ## %bb.0: 142; AVX-NEXT: vpmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero 143; AVX-NEXT: retq 144 %1 = load <16 x i8>, <16 x i8>* %a, align 1 145 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <2 x i32> <i32 0, i32 1> 146 %3 = zext <2 x i8> %2 to <2 x i64> 147 ret <2 x i64> %3 148} 149 150define <4 x i32> @test_llvm_x86_sse41_pmovzxwd(<8 x i16>* %a) { 151; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwd: 152; SSE41: ## %bb.0: 153; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero 154; SSE41-NEXT: retq 155; 156; AVX-LABEL: test_llvm_x86_sse41_pmovzxwd: 157; AVX: ## %bb.0: 158; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero 159; AVX-NEXT: retq 160 %1 = load <8 x i16>, <8 x i16>* %a, align 1 161 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 162 %3 = zext <4 x i16> %2 to <4 x i32> 163 ret <4 x i32> %3 164} 165 166define <2 x i64> @test_llvm_x86_sse41_pmovzxwq(<8 x i16>* %a) { 167; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwq: 168; SSE41: ## %bb.0: 169; SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero 170; SSE41-NEXT: retq 171; 172; AVX-LABEL: test_llvm_x86_sse41_pmovzxwq: 173; AVX: ## %bb.0: 174; AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero 175; AVX-NEXT: retq 176 %1 = load <8 x i16>, <8 x i16>* %a, align 1 177 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <2 x i32> <i32 0, i32 1> 178 %3 = zext <2 x i16> %2 to <2 x i64> 179 ret <2 x i64> %3 180} 181 182define <2 x i64> @test_llvm_x86_sse41_pmovzxdq(<4 x i32>* %a) { 183; SSE41-LABEL: test_llvm_x86_sse41_pmovzxdq: 184; SSE41: ## %bb.0: 185; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero 186; SSE41-NEXT: retq 187; 188; AVX-LABEL: test_llvm_x86_sse41_pmovzxdq: 189; AVX: ## %bb.0: 190; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero 191; AVX-NEXT: retq 192 %1 = load <4 x i32>, <4 x i32>* %a, align 1 193 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1> 194 %3 = zext <2 x i32> %2 to <2 x i64> 195 ret <2 x i64> %3 196} 197