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1; RUN: llc < %s -mtriple=x86_64-apple-macosx10.10.0 -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE2
2; RUN: llc < %s -mtriple=x86_64-apple-macosx10.10.0 -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX
3
4; Assertions have been enhanced from utils/update_llc_test_checks.py to show the constant pool values.
5; Use a macosx triple to make sure the format of those constant strings is exact.
6
7; CHECK:       [[SIGNMASK1:L.+]]:
8; CHECK-NEXT:  .long 0x80000000
9; CHECK-NEXT:  .long 0x80000000
10; CHECK-NEXT:  .long 0x80000000
11; CHECK-NEXT:  .long 0x80000000
12
13; CHECK:       [[MAGMASK1:L.+]]:
14; CHECK-NEXT:  .long 0x7fffffff
15; CHECK-NEXT:  .long 0x7fffffff
16; CHECK-NEXT:  .long 0x7fffffff
17; CHECK-NEXT:  .long 0x7fffffff
18
19define <4 x float> @v4f32(<4 x float> %a, <4 x float> %b) nounwind {
20; SSE2-LABEL: v4f32:
21; SSE2:       # %bb.0:
22; SSE2-NEXT:    andps [[SIGNMASK1]](%rip), %xmm1
23; SSE2-NEXT:    andps [[MAGMASK1]](%rip), %xmm0
24; SSE2-NEXT:    orps %xmm1, %xmm0
25; SSE2-NEXT:    retq
26;
27; AVX-LABEL: v4f32:
28; AVX:       # %bb.0:
29; AVX-NEXT:    vandps [[SIGNMASK1]](%rip), %xmm1, %xmm1
30; AVX-NEXT:    vandps [[MAGMASK1]](%rip), %xmm0, %xmm0
31; AVX-NEXT:    vorps %xmm1, %xmm0, %xmm0
32; AVX-NEXT:    retq
33;
34  %tmp = tail call <4 x float> @llvm.copysign.v4f32( <4 x float> %a, <4 x float> %b )
35  ret <4 x float> %tmp
36}
37
38; SSE2:       [[MAGMASK2:L.+]]:
39; SSE2-NEXT:  .long 0x7fffffff
40; SSE2-NEXT:  .long 0x7fffffff
41; SSE2-NEXT:  .long 0x7fffffff
42; SSE2-NEXT:  .long 0x7fffffff
43
44; AVX:       [[SIGNMASK2:L.+]]:
45; AVX-NEXT:  .long 0x80000000
46; AVX-NEXT:  .long 0x80000000
47; AVX-NEXT:  .long 0x80000000
48; AVX-NEXT:  .long 0x80000000
49; AVX-NEXT:  .long 0x80000000
50; AVX-NEXT:  .long 0x80000000
51; AVX-NEXT:  .long 0x80000000
52; AVX-NEXT:  .long 0x80000000
53
54; AVX:       [[MAGMASK2:L.+]]:
55; AVX-NEXT:  .long 0x7fffffff
56; AVX-NEXT:  .long 0x7fffffff
57; AVX-NEXT:  .long 0x7fffffff
58; AVX-NEXT:  .long 0x7fffffff
59; AVX-NEXT:  .long 0x7fffffff
60; AVX-NEXT:  .long 0x7fffffff
61; AVX-NEXT:  .long 0x7fffffff
62; AVX-NEXT:  .long 0x7fffffff
63
64define <8 x float> @v8f32(<8 x float> %a, <8 x float> %b) nounwind {
65; SSE2-LABEL: v8f32:
66; SSE2:       # %bb.0:
67; SSE2-NEXT:    movaps [[MAGMASK2]](%rip), %xmm4
68; SSE2-NEXT:    movaps %xmm4, %xmm5
69; SSE2-NEXT:    andnps %xmm2, %xmm5
70; SSE2-NEXT:    andps %xmm4, %xmm0
71; SSE2-NEXT:    orps %xmm5, %xmm0
72; SSE2-NEXT:    andps %xmm4, %xmm1
73; SSE2-NEXT:    andnps %xmm3, %xmm4
74; SSE2-NEXT:    orps %xmm4, %xmm1
75; SSE2-NEXT:    retq
76;
77; AVX-LABEL: v8f32:
78; AVX:       # %bb.0:
79; AVX-NEXT:    vandps [[SIGNMASK2]](%rip), %ymm1, %ymm1
80; AVX-NEXT:    vandps [[MAGMASK2]](%rip), %ymm0, %ymm0
81; AVX-NEXT:    vorps %ymm1, %ymm0, %ymm0
82; AVX-NEXT:    retq
83;
84  %tmp = tail call <8 x float> @llvm.copysign.v8f32( <8 x float> %a, <8 x float> %b )
85  ret <8 x float> %tmp
86}
87
88; CHECK:        [[SIGNMASK3:L.+]]:
89; CHECK-NEXT:   .quad 0x8000000000000000
90; CHECK-NEXT:   .quad 0x8000000000000000
91
92; CHECK:        [[MAGMASK3:L.+]]:
93; CHECK-NEXT:   .quad 0x7fffffffffffffff
94; CHECK-NEXT:   .quad 0x7fffffffffffffff
95
96define <2 x double> @v2f64(<2 x double> %a, <2 x double> %b) nounwind {
97; SSE2-LABEL: v2f64:
98; SSE2:       # %bb.0:
99; SSE2-NEXT:    andps [[SIGNMASK3]](%rip), %xmm1
100; SSE2-NEXT:    andps [[MAGMASK3]](%rip), %xmm0
101; SSE2-NEXT:    orps %xmm1, %xmm0
102; SSE2-NEXT:    retq
103;
104; AVX-LABEL: v2f64:
105; AVX:       # %bb.0:
106; AVX-NEXT:    vandps [[SIGNMASK3]](%rip), %xmm1, %xmm1
107; AVX-NEXT:    vandps [[MAGMASK3]](%rip), %xmm0, %xmm0
108; AVX-NEXT:    vorps %xmm1, %xmm0, %xmm0
109; AVX-NEXT:    retq
110;
111  %tmp = tail call <2 x double> @llvm.copysign.v2f64( <2 x double> %a, <2 x double> %b )
112  ret <2 x double> %tmp
113}
114
115; SSE2:        [[MAGMASK4:L.+]]:
116; SSE2-NEXT:   .quad 0x7fffffffffffffff
117; SSE2-NEXT:   .quad 0x7fffffffffffffff
118
119; AVX:        [[SIGNMASK4:L.+]]:
120; AVX-NEXT:   .quad 0x8000000000000000
121; AVX-NEXT:   .quad 0x8000000000000000
122; AVX-NEXT:   .quad 0x8000000000000000
123; AVX-NEXT:   .quad 0x8000000000000000
124
125; AVX:        [[MAGMASK4:L.+]]:
126; AVX-NEXT:   .quad 0x7fffffffffffffff
127; AVX-NEXT:   .quad 0x7fffffffffffffff
128; AVX-NEXT:   .quad 0x7fffffffffffffff
129; AVX-NEXT:   .quad 0x7fffffffffffffff
130
131define <4 x double> @v4f64(<4 x double> %a, <4 x double> %b) nounwind {
132; SSE2-LABEL: v4f64:
133; SSE2:       # %bb.0:
134; SSE2-NEXT:    movaps [[MAGMASK4]](%rip), %xmm4
135; SSE2-NEXT:    movaps %xmm4, %xmm5
136; SSE2-NEXT:    andnps %xmm2, %xmm5
137; SSE2-NEXT:    andps %xmm4, %xmm0
138; SSE2-NEXT:    orps %xmm5, %xmm0
139; SSE2-NEXT:    andps %xmm4, %xmm1
140; SSE2-NEXT:    andnps %xmm3, %xmm4
141; SSE2-NEXT:    orps %xmm4, %xmm1
142; SSE2-NEXT:    retq
143;
144; AVX-LABEL: v4f64:
145; AVX:       # %bb.0:
146; AVX-NEXT:    vandps [[SIGNMASK4]](%rip), %ymm1, %ymm1
147; AVX-NEXT:    vandps [[MAGMASK4]](%rip), %ymm0, %ymm0
148; AVX-NEXT:    vorps %ymm1, %ymm0, %ymm0
149; AVX-NEXT:    retq
150;
151  %tmp = tail call <4 x double> @llvm.copysign.v4f64( <4 x double> %a, <4 x double> %b )
152  ret <4 x double> %tmp
153}
154
155declare <4 x float>     @llvm.copysign.v4f32(<4 x float>  %Mag, <4 x float>  %Sgn)
156declare <8 x float>     @llvm.copysign.v8f32(<8 x float>  %Mag, <8 x float>  %Sgn)
157declare <2 x double>    @llvm.copysign.v2f64(<2 x double> %Mag, <2 x double> %Sgn)
158declare <4 x double>    @llvm.copysign.v4f64(<4 x double> %Mag, <4 x double> %Sgn)
159
160