1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s 3 4; Verify that for the architectures that are known to have poor latency 5; double precision shift instructions we generate alternative sequence 6; of instructions with lower latencies instead of shld instruction. 7 8;uint64_t lshift1(uint64_t a, uint64_t b) 9;{ 10; return (a << 1) | (b >> 63); 11;} 12 13define i64 @lshift1(i64 %a, i64 %b) nounwind readnone uwtable { 14; CHECK-LABEL: lshift1: 15; CHECK: # %bb.0: # %entry 16; CHECK-NEXT: shrq $63, %rsi 17; CHECK-NEXT: leaq (%rsi,%rdi,2), %rax 18; CHECK-NEXT: retq 19entry: 20 %shl = shl i64 %a, 1 21 %shr = lshr i64 %b, 63 22 %or = or i64 %shr, %shl 23 ret i64 %or 24} 25 26;uint64_t lshift2(uint64_t a, uint64_t b) 27;{ 28; return (a << 2) | (b >> 62); 29;} 30 31define i64 @lshift2(i64 %a, i64 %b) nounwind readnone uwtable { 32; CHECK-LABEL: lshift2: 33; CHECK: # %bb.0: # %entry 34; CHECK-NEXT: shrq $62, %rsi 35; CHECK-NEXT: leaq (%rsi,%rdi,4), %rax 36; CHECK-NEXT: retq 37entry: 38 %shl = shl i64 %a, 2 39 %shr = lshr i64 %b, 62 40 %or = or i64 %shr, %shl 41 ret i64 %or 42} 43 44;uint64_t lshift7(uint64_t a, uint64_t b) 45;{ 46; return (a << 7) | (b >> 57); 47;} 48 49define i64 @lshift7(i64 %a, i64 %b) nounwind readnone uwtable { 50; CHECK-LABEL: lshift7: 51; CHECK: # %bb.0: # %entry 52; CHECK-NEXT: shrq $57, %rsi 53; CHECK-NEXT: shlq $7, %rdi 54; CHECK-NEXT: leaq (%rdi,%rsi), %rax 55; CHECK-NEXT: retq 56entry: 57 %shl = shl i64 %a, 7 58 %shr = lshr i64 %b, 57 59 %or = or i64 %shr, %shl 60 ret i64 %or 61} 62 63;uint64_t lshift63(uint64_t a, uint64_t b) 64;{ 65; return (a << 63) | (b >> 1); 66;} 67 68define i64 @lshift63(i64 %a, i64 %b) nounwind readnone uwtable { 69; CHECK-LABEL: lshift63: 70; CHECK: # %bb.0: # %entry 71; CHECK-NEXT: shrq %rsi 72; CHECK-NEXT: shlq $63, %rdi 73; CHECK-NEXT: leaq (%rdi,%rsi), %rax 74; CHECK-NEXT: retq 75entry: 76 %shl = shl i64 %a, 63 77 %shr = lshr i64 %b, 1 78 %or = or i64 %shr, %shl 79 ret i64 %or 80} 81