1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s 2 3 4// ------------------------------------------------------------------------- // 5// Invalid element widths. 6 7splice z0.b, p0, { z1.h, z2.h } 8// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 9// CHECK-NEXT: splice z0.b, p0, { z1.h, z2.h } 10// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 11 12 13// --------------------------------------------------------------------------// 14// Invalid vector list. 15 16splice z0.b, p0, { } 17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected 18// CHECK-NEXT: splice z0.b, p0, { } 19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 20 21splice z0.b, p0, { z1.b } 22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 23// CHECK-NEXT: splice z0.b, p0, { z1.b } 24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 25 26splice z0.b, p0, { z1.b, z2.b, z3.b } 27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 28// CHECK-NEXT: splice z0.b, p0, { z1.b, z2.b, z3.b } 29// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 30 31splice z0.b, p0, { z1.b, z2.h } 32// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix 33// CHECK-NEXT: splice z0.b, p0, { z1.b, z2.h } 34// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 35 36splice z0.b, p0, { z1.b, z31.b } 37// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential 38// CHECK-NEXT: splice z0.b, p0, { z1.b, z31.b } 39// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 40 41splice z0.b, p0, { v0.4b, v1.4b } 42// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 43// CHECK-NEXT: splice z0.b, p0, { v0.4b, v1.4b } 44// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 45 46 47// --------------------------------------------------------------------------// 48// Invalid predicate operation 49 50splice z0.b, p0/z, { z1.b, z2.b } 51// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected 52// CHECK-NEXT: splice z0.b, p0/z, { z1.b, z2.b } 53// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 54 55splice z0.b, p0/m, { z1.b, z2.b } 56// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected 57// CHECK-NEXT: splice z0.b, p0/m, { z1.b, z2.b } 58// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 59 60 61// --------------------------------------------------------------------------// 62// Predicate not in restricted predicate range 63 64splice z0.b, p8, { z1.b, z2.b } 65// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) 66// CHECK-NEXT: splice z0.b, p8, { z1.b, z2.b } 67// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 68 69 70// --------------------------------------------------------------------------// 71// Negative tests for instructions that are incompatible with movprfx 72 73movprfx z31, z6 74splice z31.b, p0, { z30.b, z31.b } 75// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 76// CHECK-NEXT: splice z31.b, p0, { z30.b, z31.b } 77// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 78 79movprfx z31.b, p0/z, z6.b 80splice z31.b, p0, { z30.b, z31.b } 81// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 82// CHECK-NEXT: splice z31.b, p0, { z30.b, z31.b } 83// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 84