1# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s 2# RUN: llvm-mc -triple arm64-none-linux-gnu -disassemble < %s | FileCheck %s 3 40x8 0xcc 0x38 0xd5 5# CHECK: mrs x8, {{icc_iar1_el1|ICC_IAR1_EL1}} 60x1a 0xc8 0x38 0xd5 7# CHECK: mrs x26, {{icc_iar0_el1|ICC_IAR0_EL1}} 80x42 0xcc 0x38 0xd5 9# CHECK: mrs x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}} 100x51 0xc8 0x38 0xd5 11# CHECK: mrs x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}} 120x7d 0xcb 0x38 0xd5 13# CHECK: mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}} 140x24 0xcb 0x3c 0xd5 15# CHECK: mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}} 160x78 0xcb 0x3c 0xd5 17# CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}} 180xa9 0xcb 0x3c 0xd5 19# CHECK: mrs x9, {{ich_elrsr_el2|ICH_ELRSR_EL2}} 200x78 0xcc 0x38 0xd5 21# CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}} 220x6e 0xc8 0x38 0xd5 23# CHECK: mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}} 240x13 0x46 0x38 0xd5 25# CHECK: mrs x19, {{icc_pmr_el1|ICC_PMR_EL1}} 260x97 0xcc 0x38 0xd5 27# CHECK: mrs x23, {{icc_ctlr_el1|ICC_CTLR_EL1}} 280x94 0xcc 0x3e 0xd5 29# CHECK: mrs x20, {{icc_ctlr_el3|ICC_CTLR_EL3}} 300xbc 0xcc 0x38 0xd5 31# CHECK: mrs x28, {{icc_sre_el1|ICC_SRE_EL1}} 320xb9 0xc9 0x3c 0xd5 33# CHECK: mrs x25, {{icc_sre_el2|ICC_SRE_EL2}} 340xa8 0xcc 0x3e 0xd5 35# CHECK: mrs x8, {{icc_sre_el3|ICC_SRE_EL3}} 360xd6 0xcc 0x38 0xd5 37# CHECK: mrs x22, {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}} 380xe5 0xcc 0x38 0xd5 39# CHECK: mrs x5, {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}} 400xe7 0xcc 0x3e 0xd5 41# CHECK: mrs x7, {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}} 420x84 0xc8 0x38 0xd5 43# CHECK: mrs x4, {{icc_ap0r0_el1|ICC_AP0R0_EL1}} 440xab 0xc8 0x38 0xd5 45# CHECK: mrs x11, {{icc_ap0r1_el1|ICC_AP0R1_EL1}} 460xdb 0xc8 0x38 0xd5 47# CHECK: mrs x27, {{icc_ap0r2_el1|ICC_AP0R2_EL1}} 480xf5 0xc8 0x38 0xd5 49# CHECK: mrs x21, {{icc_ap0r3_el1|ICC_AP0R3_EL1}} 500x2 0xc9 0x38 0xd5 51# CHECK: mrs x2, {{icc_ap1r0_el1|ICC_AP1R0_EL1}} 520x35 0xc9 0x38 0xd5 53# CHECK: mrs x21, {{icc_ap1r1_el1|ICC_AP1R1_EL1}} 540x4a 0xc9 0x38 0xd5 55# CHECK: mrs x10, {{icc_ap1r2_el1|ICC_AP1R2_EL1}} 560x7b 0xc9 0x38 0xd5 57# CHECK: mrs x27, {{icc_ap1r3_el1|ICC_AP1R3_EL1}} 580x14 0xc8 0x3c 0xd5 59# CHECK: mrs x20, {{ich_ap0r0_el2|ICH_AP0R0_EL2}} 600x35 0xc8 0x3c 0xd5 61# CHECK: mrs x21, {{ich_ap0r1_el2|ICH_AP0R1_EL2}} 620x45 0xc8 0x3c 0xd5 63# CHECK: mrs x5, {{ich_ap0r2_el2|ICH_AP0R2_EL2}} 640x64 0xc8 0x3c 0xd5 65# CHECK: mrs x4, {{ich_ap0r3_el2|ICH_AP0R3_EL2}} 660xf 0xc9 0x3c 0xd5 67# CHECK: mrs x15, {{ich_ap1r0_el2|ICH_AP1R0_EL2}} 680x2c 0xc9 0x3c 0xd5 69# CHECK: mrs x12, {{ich_ap1r1_el2|ICH_AP1R1_EL2}} 700x5b 0xc9 0x3c 0xd5 71# CHECK: mrs x27, {{ich_ap1r2_el2|ICH_AP1R2_EL2}} 720x74 0xc9 0x3c 0xd5 73# CHECK: mrs x20, {{ich_ap1r3_el2|ICH_AP1R3_EL2}} 740xa 0xcb 0x3c 0xd5 75# CHECK: mrs x10, {{ich_hcr_el2|ICH_HCR_EL2}} 760x5b 0xcb 0x3c 0xd5 77# CHECK: mrs x27, {{ich_misr_el2|ICH_MISR_EL2}} 780xe6 0xcb 0x3c 0xd5 79# CHECK: mrs x6, {{ich_vmcr_el2|ICH_VMCR_EL2}} 800x3 0xcc 0x3c 0xd5 81# CHECK: mrs x3, {{ich_lr0_el2|ICH_LR0_EL2}} 820x21 0xcc 0x3c 0xd5 83# CHECK: mrs x1, {{ich_lr1_el2|ICH_LR1_EL2}} 840x56 0xcc 0x3c 0xd5 85# CHECK: mrs x22, {{ich_lr2_el2|ICH_LR2_EL2}} 860x75 0xcc 0x3c 0xd5 87# CHECK: mrs x21, {{ich_lr3_el2|ICH_LR3_EL2}} 880x86 0xcc 0x3c 0xd5 89# CHECK: mrs x6, {{ich_lr4_el2|ICH_LR4_EL2}} 900xaa 0xcc 0x3c 0xd5 91# CHECK: mrs x10, {{ich_lr5_el2|ICH_LR5_EL2}} 920xcb 0xcc 0x3c 0xd5 93# CHECK: mrs x11, {{ich_lr6_el2|ICH_LR6_EL2}} 940xec 0xcc 0x3c 0xd5 95# CHECK: mrs x12, {{ich_lr7_el2|ICH_LR7_EL2}} 960x0 0xcd 0x3c 0xd5 97# CHECK: mrs x0, {{ich_lr8_el2|ICH_LR8_EL2}} 980x35 0xcd 0x3c 0xd5 99# CHECK: mrs x21, {{ich_lr9_el2|ICH_LR9_EL2}} 1000x4d 0xcd 0x3c 0xd5 101# CHECK: mrs x13, {{ich_lr10_el2|ICH_LR10_EL2}} 1020x7a 0xcd 0x3c 0xd5 103# CHECK: mrs x26, {{ich_lr11_el2|ICH_LR11_EL2}} 1040x81 0xcd 0x3c 0xd5 105# CHECK: mrs x1, {{ich_lr12_el2|ICH_LR12_EL2}} 1060xa8 0xcd 0x3c 0xd5 107# CHECK: mrs x8, {{ich_lr13_el2|ICH_LR13_EL2}} 1080xc2 0xcd 0x3c 0xd5 109# CHECK: mrs x2, {{ich_lr14_el2|ICH_LR14_EL2}} 1100xe8 0xcd 0x3c 0xd5 111# CHECK: mrs x8, {{ich_lr15_el2|ICH_LR15_EL2}} 1120x3b 0xcc 0x18 0xd5 113# CHECK: msr {{icc_eoir1_el1|ICC_EOIR1_EL1}}, x27 1140x25 0xc8 0x18 0xd5 115# CHECK: msr {{icc_eoir0_el1|ICC_EOIR0_EL1}}, x5 1160x2d 0xcb 0x18 0xd5 117# CHECK: msr {{icc_dir_el1|ICC_DIR_EL1}}, x13 1180xb5 0xcb 0x18 0xd5 119# CHECK: msr {{icc_sgi1r_el1|ICC_SGI1R_EL1}}, x21 1200xd9 0xcb 0x18 0xd5 121# CHECK: msr {{icc_asgi1r_el1|ICC_ASGI1R_EL1}}, x25 1220xfc 0xcb 0x18 0xd5 123# CHECK: msr {{icc_sgi0r_el1|ICC_SGI0R_EL1}}, x28 1240x67 0xcc 0x18 0xd5 125# CHECK: msr {{icc_bpr1_el1|ICC_BPR1_EL1}}, x7 1260x69 0xc8 0x18 0xd5 127# CHECK: msr {{icc_bpr0_el1|ICC_BPR0_EL1}}, x9 1280x1d 0x46 0x18 0xd5 129# CHECK: msr {{icc_pmr_el1|ICC_PMR_EL1}}, x29 1300x98 0xcc 0x18 0xd5 131# CHECK: msr {{icc_ctlr_el1|ICC_CTLR_EL1}}, x24 1320x80 0xcc 0x1e 0xd5 133# CHECK: msr {{icc_ctlr_el3|ICC_CTLR_EL3}}, x0 1340xa2 0xcc 0x18 0xd5 135# CHECK: msr {{icc_sre_el1|ICC_SRE_EL1}}, x2 1360xa5 0xc9 0x1c 0xd5 137# CHECK: msr {{icc_sre_el2|ICC_SRE_EL2}}, x5 1380xaa 0xcc 0x1e 0xd5 139# CHECK: msr {{icc_sre_el3|ICC_SRE_EL3}}, x10 1400xd6 0xcc 0x18 0xd5 141# CHECK: msr {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x22 1420xeb 0xcc 0x18 0xd5 143# CHECK: msr {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}, x11 1440xe8 0xcc 0x1e 0xd5 145# CHECK: msr {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}, x8 1460x9b 0xc8 0x18 0xd5 147# CHECK: msr {{icc_ap0r0_el1|ICC_AP0R0_EL1}}, x27 1480xa5 0xc8 0x18 0xd5 149# CHECK: msr {{icc_ap0r1_el1|ICC_AP0R1_EL1}}, x5 1500xd4 0xc8 0x18 0xd5 151# CHECK: msr {{icc_ap0r2_el1|ICC_AP0R2_EL1}}, x20 1520xe0 0xc8 0x18 0xd5 153# CHECK: msr {{icc_ap0r3_el1|ICC_AP0R3_EL1}}, x0 1540x2 0xc9 0x18 0xd5 155# CHECK: msr {{icc_ap1r0_el1|ICC_AP1R0_EL1}}, x2 1560x3d 0xc9 0x18 0xd5 157# CHECK: msr {{icc_ap1r1_el1|ICC_AP1R1_EL1}}, x29 1580x57 0xc9 0x18 0xd5 159# CHECK: msr {{icc_ap1r2_el1|ICC_AP1R2_EL1}}, x23 1600x6b 0xc9 0x18 0xd5 161# CHECK: msr {{icc_ap1r3_el1|ICC_AP1R3_EL1}}, x11 1620x2 0xc8 0x1c 0xd5 163# CHECK: msr {{ich_ap0r0_el2|ICH_AP0R0_EL2}}, x2 1640x3b 0xc8 0x1c 0xd5 165# CHECK: msr {{ich_ap0r1_el2|ICH_AP0R1_EL2}}, x27 1660x47 0xc8 0x1c 0xd5 167# CHECK: msr {{ich_ap0r2_el2|ICH_AP0R2_EL2}}, x7 1680x61 0xc8 0x1c 0xd5 169# CHECK: msr {{ich_ap0r3_el2|ICH_AP0R3_EL2}}, x1 1700x7 0xc9 0x1c 0xd5 171# CHECK: msr {{ich_ap1r0_el2|ICH_AP1R0_EL2}}, x7 1720x2c 0xc9 0x1c 0xd5 173# CHECK: msr {{ich_ap1r1_el2|ICH_AP1R1_EL2}}, x12 1740x4e 0xc9 0x1c 0xd5 175# CHECK: msr {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x14 1760x6d 0xc9 0x1c 0xd5 177# CHECK: msr {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x13 1780x1 0xcb 0x1c 0xd5 179# CHECK: msr {{ich_hcr_el2|ICH_HCR_EL2}}, x1 1800x4a 0xcb 0x1c 0xd5 181# CHECK: msr S3_4_C12_C11_2, x10 1820xf8 0xcb 0x1c 0xd5 183# CHECK: msr {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24 1840x1a 0xcc 0x1c 0xd5 185# CHECK: msr {{ich_lr0_el2|ICH_LR0_EL2}}, x26 1860x29 0xcc 0x1c 0xd5 187# CHECK: msr {{ich_lr1_el2|ICH_LR1_EL2}}, x9 1880x52 0xcc 0x1c 0xd5 189# CHECK: msr {{ich_lr2_el2|ICH_LR2_EL2}}, x18 1900x7a 0xcc 0x1c 0xd5 191# CHECK: msr {{ich_lr3_el2|ICH_LR3_EL2}}, x26 1920x96 0xcc 0x1c 0xd5 193# CHECK: msr {{ich_lr4_el2|ICH_LR4_EL2}}, x22 1940xba 0xcc 0x1c 0xd5 195# CHECK: msr {{ich_lr5_el2|ICH_LR5_EL2}}, x26 1960xdb 0xcc 0x1c 0xd5 197# CHECK: msr {{ich_lr6_el2|ICH_LR6_EL2}}, x27 1980xe8 0xcc 0x1c 0xd5 199# CHECK: msr {{ich_lr7_el2|ICH_LR7_EL2}}, x8 2000x11 0xcd 0x1c 0xd5 201# CHECK: msr {{ich_lr8_el2|ICH_LR8_EL2}}, x17 2020x33 0xcd 0x1c 0xd5 203# CHECK: msr {{ich_lr9_el2|ICH_LR9_EL2}}, x19 2040x51 0xcd 0x1c 0xd5 205# CHECK: msr {{ich_lr10_el2|ICH_LR10_EL2}}, x17 2060x65 0xcd 0x1c 0xd5 207# CHECK: msr {{ich_lr11_el2|ICH_LR11_EL2}}, x5 2080x9d 0xcd 0x1c 0xd5 209# CHECK: msr {{ich_lr12_el2|ICH_LR12_EL2}}, x29 2100xa2 0xcd 0x1c 0xd5 211# CHECK: msr {{ich_lr13_el2|ICH_LR13_EL2}}, x2 2120xcd 0xcd 0x1c 0xd5 213# CHECK: msr {{ich_lr14_el2|ICH_LR14_EL2}}, x13 2140xfb 0xcd 0x1c 0xd5 215# CHECK: msr {{ich_lr15_el2|ICH_LR15_EL2}}, x27 216