1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -bdce < %s | FileCheck %s 3define i32 @ZEXT_0(i16 %a) { 4; CHECK-LABEL: @ZEXT_0( 5; CHECK-NEXT: entry: 6; CHECK-NEXT: [[EXT1:%.*]] = zext i16 [[A:%.*]] to i32 7; CHECK-NEXT: [[AND:%.*]] = and i32 [[EXT1]], 65280 8; CHECK-NEXT: [[LSR:%.*]] = lshr i32 [[EXT1]], 8 9; CHECK-NEXT: [[AND2:%.*]] = and i32 [[LSR]], 255 10; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND2]] 11; CHECK-NEXT: ret i32 [[OR]] 12; 13entry: 14 %ext = sext i16 %a to i32 15 %and = and i32 %ext, 65280 16 %lsr = lshr i32 %ext, 8 17 %and2 = and i32 %lsr, 255 18 %or = or i32 %and, %and2 19 ret i32 %or 20} 21 22define i32 @ZEXT_1(i16 %a) { 23; CHECK-LABEL: @ZEXT_1( 24; CHECK-NEXT: entry: 25; CHECK-NEXT: [[EXT1:%.*]] = zext i16 [[A:%.*]] to i32 26; CHECK-NEXT: [[LSR:%.*]] = lshr i32 [[EXT1]], 8 27; CHECK-NEXT: [[AND2:%.*]] = and i32 [[LSR]], 255 28; CHECK-NEXT: [[AND:%.*]] = or i32 [[EXT1]], -65536 29; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND2]] 30; CHECK-NEXT: ret i32 [[OR]] 31; 32entry: 33 %ext = sext i16 %a to i32 34 %lsr = lshr i32 %ext, 8 35 %and2 = and i32 %lsr, 255 36 %and = or i32 %ext, 4294901760 37 %or = or i32 %and, %and2 38 ret i32 %or 39} 40 41define i16 @NOT_ZEXT_0(i16 %a) { 42; CHECK-LABEL: @NOT_ZEXT_0( 43; CHECK-NEXT: entry: 44; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[A:%.*]] to i32 45; CHECK-NEXT: [[AND:%.*]] = and i32 [[EXT]], 65280 46; CHECK-NEXT: [[LSR:%.*]] = lshr i32 [[EXT]], 9 47; CHECK-NEXT: [[AND2:%.*]] = and i32 [[LSR]], 255 48; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND2]] 49; CHECK-NEXT: [[RET:%.*]] = trunc i32 [[OR]] to i16 50; CHECK-NEXT: ret i16 [[RET]] 51; 52entry: 53 %ext = sext i16 %a to i32 54 %and = and i32 %ext, 65280 55 %lsr = lshr i32 %ext, 9 56 %and2 = and i32 %lsr, 255 57 %or = or i32 %and, %and2 58 %ret = trunc i32 %or to i16 59 ret i16 %ret 60} 61 62define i32 @NOT_ZEXT_1(i16 %a) { 63; CHECK-LABEL: @NOT_ZEXT_1( 64; CHECK-NEXT: entry: 65; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[A:%.*]] to i32 66; CHECK-NEXT: [[AND:%.*]] = and i32 [[EXT]], 85280 67; CHECK-NEXT: [[LSR:%.*]] = lshr i32 [[EXT]], 8 68; CHECK-NEXT: [[AND2:%.*]] = and i32 [[LSR]], 255 69; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND2]] 70; CHECK-NEXT: ret i32 [[OR]] 71; 72entry: 73 %ext = sext i16 %a to i32 74 %and = and i32 %ext, 85280 75 %lsr = lshr i32 %ext, 8 76 %and2 = and i32 %lsr, 255 77 %or = or i32 %and, %and2 78 ret i32 %or 79} 80 81define i32 @NOT_ZEXT_2(i16 %a) { 82; CHECK-LABEL: @NOT_ZEXT_2( 83; CHECK-NEXT: entry: 84; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[A:%.*]] to i32 85; CHECK-NEXT: [[LSR:%.*]] = lshr i32 [[EXT]], 8 86; CHECK-NEXT: [[AND2:%.*]] = and i32 [[LSR]], 255 87; CHECK-NEXT: [[AND:%.*]] = xor i32 [[EXT]], -65536 88; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND2]] 89; CHECK-NEXT: ret i32 [[OR]] 90; 91entry: 92 %ext = sext i16 %a to i32 93 %lsr = lshr i32 %ext, 8 94 %and2 = and i32 %lsr, 255 95 %and = xor i32 %ext, 4294901760 96 %or = or i32 %and, %and2 97 ret i32 %or 98} 99 100define i16 @clear_assumptions(i8 %x, i16 %y) { 101; CHECK-LABEL: @clear_assumptions( 102; CHECK-NEXT: [[EXT1:%.*]] = zext i8 [[X:%.*]] to i16 103; CHECK-NEXT: [[ADD:%.*]] = add i16 [[EXT1]], [[Y:%.*]] 104; CHECK-NEXT: [[AND:%.*]] = and i16 [[ADD]], 255 105; CHECK-NEXT: ret i16 [[AND]] 106; 107 %ext = sext i8 %x to i16 108 %add = add nsw i16 %ext, %y 109 %and = and i16 %add, 255 110 ret i16 %and 111} 112