1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -instcombine -S | FileCheck %s 3 4; Instcombine should recognize that this code can be adjusted to fit the canonical max/min pattern. 5 6; No change 7 8define i32 @smax1(i32 %n) { 9; CHECK-LABEL: @smax1( 10; CHECK-NEXT: [[T:%.*]] = icmp sgt i32 [[N:%.*]], 0 11; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 [[N]], i32 0 12; CHECK-NEXT: ret i32 [[M]] 13; 14 %t = icmp sgt i32 %n, 0 15 %m = select i1 %t, i32 %n, i32 0 16 ret i32 %m 17} 18 19; No change 20 21define i32 @smin1(i32 %n) { 22; CHECK-LABEL: @smin1( 23; CHECK-NEXT: [[T:%.*]] = icmp slt i32 [[N:%.*]], 0 24; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 [[N]], i32 0 25; CHECK-NEXT: ret i32 [[M]] 26; 27 %t = icmp slt i32 %n, 0 28 %m = select i1 %t, i32 %n, i32 0 29 ret i32 %m 30} 31 32; Canonicalize min/max. 33 34define i32 @smax2(i32 %n) { 35; CHECK-LABEL: @smax2( 36; CHECK-NEXT: [[T:%.*]] = icmp sgt i32 [[N:%.*]], 0 37; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 [[N]], i32 0 38; CHECK-NEXT: ret i32 [[M]] 39; 40 %t = icmp sge i32 %n, 1 41 %m = select i1 %t, i32 %n, i32 0 42 ret i32 %m 43} 44 45; Canonicalize min/max. 46 47define i32 @smin2(i32 %n) { 48; CHECK-LABEL: @smin2( 49; CHECK-NEXT: [[T:%.*]] = icmp slt i32 [[N:%.*]], 0 50; CHECK-NEXT: [[M:%.*]] = select i1 [[T]], i32 [[N]], i32 0 51; CHECK-NEXT: ret i32 [[M]] 52; 53 %t = icmp sle i32 %n, -1 54 %m = select i1 %t, i32 %n, i32 0 55 ret i32 %m 56} 57 58; Canonicalize min/max. 59 60define i32 @smax3(i32 %n) { 61; CHECK-LABEL: @smax3( 62; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[N:%.*]], 0 63; CHECK-NEXT: [[M:%.*]] = select i1 [[TMP1]], i32 [[N]], i32 0 64; CHECK-NEXT: ret i32 [[M]] 65; 66 %t = icmp sgt i32 %n, -1 67 %m = select i1 %t, i32 %n, i32 0 68 ret i32 %m 69} 70 71; Canonicalize min/max. 72 73define <2 x i32> @smax3_vec(<2 x i32> %n) { 74; CHECK-LABEL: @smax3_vec( 75; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <2 x i32> [[N:%.*]], zeroinitializer 76; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[N]], <2 x i32> zeroinitializer 77; CHECK-NEXT: ret <2 x i32> [[M]] 78; 79 %t = icmp sgt <2 x i32> %n, <i32 -1, i32 -1> 80 %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer 81 ret <2 x i32> %m 82} 83 84; Canonicalize min/max. 85 86define i32 @smin3(i32 %n) { 87; CHECK-LABEL: @smin3( 88; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[N:%.*]], 0 89; CHECK-NEXT: [[M:%.*]] = select i1 [[TMP1]], i32 [[N]], i32 0 90; CHECK-NEXT: ret i32 [[M]] 91; 92 %t = icmp slt i32 %n, 1 93 %m = select i1 %t, i32 %n, i32 0 94 ret i32 %m 95} 96 97; Canonicalize min/max. 98 99define <2 x i32> @smin3_vec(<2 x i32> %n) { 100; CHECK-LABEL: @smin3_vec( 101; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i32> [[N:%.*]], zeroinitializer 102; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[N]], <2 x i32> zeroinitializer 103; CHECK-NEXT: ret <2 x i32> [[M]] 104; 105 %t = icmp slt <2 x i32> %n, <i32 1, i32 1> 106 %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer 107 ret <2 x i32> %m 108} 109 110; Canonicalize min/max. 111 112define i32 @umax3(i32 %n) { 113; CHECK-LABEL: @umax3( 114; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[N:%.*]], 5 115; CHECK-NEXT: [[M:%.*]] = select i1 [[TMP1]], i32 [[N]], i32 5 116; CHECK-NEXT: ret i32 [[M]] 117; 118 %t = icmp ugt i32 %n, 4 119 %m = select i1 %t, i32 %n, i32 5 120 ret i32 %m 121} 122 123; Canonicalize min/max. 124 125define <2 x i32> @umax3_vec(<2 x i32> %n) { 126; CHECK-LABEL: @umax3_vec( 127; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i32> [[N:%.*]], <i32 5, i32 5> 128; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[N]], <2 x i32> <i32 5, i32 5> 129; CHECK-NEXT: ret <2 x i32> [[M]] 130; 131 %t = icmp ugt <2 x i32> %n, <i32 4, i32 4> 132 %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 5, i32 5> 133 ret <2 x i32> %m 134} 135 136; Canonicalize min/max. 137 138define i32 @umin3(i32 %n) { 139; CHECK-LABEL: @umin3( 140; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[N:%.*]], 6 141; CHECK-NEXT: [[M:%.*]] = select i1 [[TMP1]], i32 [[N]], i32 6 142; CHECK-NEXT: ret i32 [[M]] 143; 144 %t = icmp ult i32 %n, 7 145 %m = select i1 %t, i32 %n, i32 6 146 ret i32 %m 147} 148 149; Canonicalize min/max. 150 151define <2 x i32> @umin3_vec(<2 x i32> %n) { 152; CHECK-LABEL: @umin3_vec( 153; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i32> [[N:%.*]], <i32 6, i32 6> 154; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[N]], <2 x i32> <i32 6, i32 6> 155; CHECK-NEXT: ret <2 x i32> [[M]] 156; 157 %t = icmp ult <2 x i32> %n, <i32 7, i32 7> 158 %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 6, i32 6> 159 ret <2 x i32> %m 160} 161 162; Canonicalize min/max. 163 164define i32 @smax4(i32 %n) { 165; CHECK-LABEL: @smax4( 166; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[N:%.*]], 0 167; CHECK-NEXT: [[M:%.*]] = select i1 [[TMP1]], i32 [[N]], i32 0 168; CHECK-NEXT: ret i32 [[M]] 169; 170 %t = icmp sge i32 %n, 0 171 %m = select i1 %t, i32 %n, i32 0 172 ret i32 %m 173} 174 175; Canonicalize min/max. 176 177define <2 x i32> @smax4_vec(<2 x i32> %n) { 178; CHECK-LABEL: @smax4_vec( 179; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <2 x i32> [[N:%.*]], zeroinitializer 180; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[N]], <2 x i32> zeroinitializer 181; CHECK-NEXT: ret <2 x i32> [[M]] 182; 183 %t = icmp sge <2 x i32> %n, zeroinitializer 184 %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer 185 ret <2 x i32> %m 186} 187 188; Canonicalize min/max. 189 190define i32 @smin4(i32 %n) { 191; CHECK-LABEL: @smin4( 192; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[N:%.*]], 0 193; CHECK-NEXT: [[M:%.*]] = select i1 [[TMP1]], i32 [[N]], i32 0 194; CHECK-NEXT: ret i32 [[M]] 195; 196 %t = icmp sle i32 %n, 0 197 %m = select i1 %t, i32 %n, i32 0 198 ret i32 %m 199} 200 201; Canonicalize min/max. 202 203define <2 x i32> @smin4_vec(<2 x i32> %n) { 204; CHECK-LABEL: @smin4_vec( 205; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i32> [[N:%.*]], zeroinitializer 206; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[N]], <2 x i32> zeroinitializer 207; CHECK-NEXT: ret <2 x i32> [[M]] 208; 209 %t = icmp sle <2 x i32> %n, zeroinitializer 210 %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer 211 ret <2 x i32> %m 212} 213 214; Canonicalize min/max. 215 216define i32 @umax4(i32 %n) { 217; CHECK-LABEL: @umax4( 218; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[N:%.*]], 8 219; CHECK-NEXT: [[M:%.*]] = select i1 [[TMP1]], i32 [[N]], i32 8 220; CHECK-NEXT: ret i32 [[M]] 221; 222 %t = icmp uge i32 %n, 8 223 %m = select i1 %t, i32 %n, i32 8 224 ret i32 %m 225} 226 227; Canonicalize min/max. 228 229define <2 x i32> @umax4_vec(<2 x i32> %n) { 230; CHECK-LABEL: @umax4_vec( 231; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i32> [[N:%.*]], <i32 8, i32 8> 232; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[N]], <2 x i32> <i32 8, i32 8> 233; CHECK-NEXT: ret <2 x i32> [[M]] 234; 235 %t = icmp uge <2 x i32> %n, <i32 8, i32 8> 236 %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 8, i32 8> 237 ret <2 x i32> %m 238} 239 240; Canonicalize min/max. 241 242define i32 @umin4(i32 %n) { 243; CHECK-LABEL: @umin4( 244; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[N:%.*]], 9 245; CHECK-NEXT: [[M:%.*]] = select i1 [[TMP1]], i32 [[N]], i32 9 246; CHECK-NEXT: ret i32 [[M]] 247; 248 %t = icmp ule i32 %n, 9 249 %m = select i1 %t, i32 %n, i32 9 250 ret i32 %m 251} 252 253; Canonicalize min/max. 254 255define <2 x i32> @umin4_vec(<2 x i32> %n) { 256; CHECK-LABEL: @umin4_vec( 257; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i32> [[N:%.*]], <i32 9, i32 9> 258; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[N]], <2 x i32> <i32 9, i32 9> 259; CHECK-NEXT: ret <2 x i32> [[M]] 260; 261 %t = icmp ule <2 x i32> %n, <i32 9, i32 9> 262 %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 9, i32 9> 263 ret <2 x i32> %m 264} 265 266define i64 @smax_sext(i32 %a) { 267; CHECK-LABEL: @smax_sext( 268; CHECK-NEXT: [[A_EXT:%.*]] = sext i32 [[A:%.*]] to i64 269; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[A_EXT]], 0 270; CHECK-NEXT: [[MAX:%.*]] = select i1 [[TMP1]], i64 [[A_EXT]], i64 0 271; CHECK-NEXT: ret i64 [[MAX]] 272; 273 %a_ext = sext i32 %a to i64 274 %cmp = icmp sgt i32 %a, -1 275 %max = select i1 %cmp, i64 %a_ext, i64 0 276 ret i64 %max 277} 278 279define <2 x i64> @smax_sext_vec(<2 x i32> %a) { 280; CHECK-LABEL: @smax_sext_vec( 281; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> [[A:%.*]] to <2 x i64> 282; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <2 x i64> [[A_EXT]], zeroinitializer 283; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[TMP1]], <2 x i64> [[A_EXT]], <2 x i64> zeroinitializer 284; CHECK-NEXT: ret <2 x i64> [[MAX]] 285; 286 %a_ext = sext <2 x i32> %a to <2 x i64> 287 %cmp = icmp sgt <2 x i32> %a, <i32 -1, i32 -1> 288 %max = select <2 x i1> %cmp, <2 x i64> %a_ext, <2 x i64> zeroinitializer 289 ret <2 x i64> %max 290} 291 292define i64 @smin_sext(i32 %a) { 293; CHECK-LABEL: @smin_sext( 294; CHECK-NEXT: [[A_EXT:%.*]] = sext i32 [[A:%.*]] to i64 295; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i64 [[A_EXT]], 0 296; CHECK-NEXT: [[MIN:%.*]] = select i1 [[TMP1]], i64 [[A_EXT]], i64 0 297; CHECK-NEXT: ret i64 [[MIN]] 298; 299 %a_ext = sext i32 %a to i64 300 %cmp = icmp slt i32 %a, 1 301 %min = select i1 %cmp, i64 %a_ext, i64 0 302 ret i64 %min 303} 304 305define <2 x i64>@smin_sext_vec(<2 x i32> %a) { 306; CHECK-LABEL: @smin_sext_vec( 307; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> [[A:%.*]] to <2 x i64> 308; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i64> [[A_EXT]], zeroinitializer 309; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[TMP1]], <2 x i64> [[A_EXT]], <2 x i64> zeroinitializer 310; CHECK-NEXT: ret <2 x i64> [[MIN]] 311; 312 %a_ext = sext <2 x i32> %a to <2 x i64> 313 %cmp = icmp slt <2 x i32> %a, <i32 1, i32 1> 314 %min = select <2 x i1> %cmp, <2 x i64> %a_ext, <2 x i64> zeroinitializer 315 ret <2 x i64> %min 316} 317 318define i64 @umax_sext(i32 %a) { 319; CHECK-LABEL: @umax_sext( 320; CHECK-NEXT: [[A_EXT:%.*]] = sext i32 [[A:%.*]] to i64 321; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[A_EXT]], 3 322; CHECK-NEXT: [[MAX:%.*]] = select i1 [[TMP1]], i64 [[A_EXT]], i64 3 323; CHECK-NEXT: ret i64 [[MAX]] 324; 325 %a_ext = sext i32 %a to i64 326 %cmp = icmp ugt i32 %a, 2 327 %max = select i1 %cmp, i64 %a_ext, i64 3 328 ret i64 %max 329} 330 331define <2 x i64> @umax_sext_vec(<2 x i32> %a) { 332; CHECK-LABEL: @umax_sext_vec( 333; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> [[A:%.*]] to <2 x i64> 334; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i64> [[A_EXT]], <i64 3, i64 3> 335; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[TMP1]], <2 x i64> [[A_EXT]], <2 x i64> <i64 3, i64 3> 336; CHECK-NEXT: ret <2 x i64> [[MAX]] 337; 338 %a_ext = sext <2 x i32> %a to <2 x i64> 339 %cmp = icmp ugt <2 x i32> %a, <i32 2, i32 2> 340 %max = select <2 x i1> %cmp, <2 x i64> %a_ext, <2 x i64> <i64 3, i64 3> 341 ret <2 x i64> %max 342} 343 344define i64 @umin_sext(i32 %a) { 345; CHECK-LABEL: @umin_sext( 346; CHECK-NEXT: [[A_EXT:%.*]] = sext i32 [[A:%.*]] to i64 347; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[A_EXT]], 2 348; CHECK-NEXT: [[MIN:%.*]] = select i1 [[TMP1]], i64 [[A_EXT]], i64 2 349; CHECK-NEXT: ret i64 [[MIN]] 350; 351 %a_ext = sext i32 %a to i64 352 %cmp = icmp ult i32 %a, 3 353 %min = select i1 %cmp, i64 %a_ext, i64 2 354 ret i64 %min 355} 356 357define <2 x i64> @umin_sext_vec(<2 x i32> %a) { 358; CHECK-LABEL: @umin_sext_vec( 359; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> [[A:%.*]] to <2 x i64> 360; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i64> [[A_EXT]], <i64 2, i64 2> 361; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[TMP1]], <2 x i64> [[A_EXT]], <2 x i64> <i64 2, i64 2> 362; CHECK-NEXT: ret <2 x i64> [[MIN]] 363; 364 %a_ext = sext <2 x i32> %a to <2 x i64> 365 %cmp = icmp ult <2 x i32> %a, <i32 3, i32 3> 366 %min = select <2 x i1> %cmp, <2 x i64> %a_ext, <2 x i64> <i64 2, i64 2> 367 ret <2 x i64> %min 368} 369 370define i64 @umax_sext2(i32 %a) { 371; CHECK-LABEL: @umax_sext2( 372; CHECK-NEXT: [[A_EXT:%.*]] = sext i32 [[A:%.*]] to i64 373; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[A_EXT]], 2 374; CHECK-NEXT: [[MIN:%.*]] = select i1 [[CMP]], i64 [[A_EXT]], i64 2 375; CHECK-NEXT: ret i64 [[MIN]] 376; 377 %a_ext = sext i32 %a to i64 378 %cmp = icmp ult i32 %a, 3 379 %min = select i1 %cmp, i64 2, i64 %a_ext 380 ret i64 %min 381} 382 383define <2 x i64> @umax_sext2_vec(<2 x i32> %a) { 384; CHECK-LABEL: @umax_sext2_vec( 385; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> [[A:%.*]] to <2 x i64> 386; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i64> [[A_EXT]], <i64 2, i64 2> 387; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 2, i64 2> 388; CHECK-NEXT: ret <2 x i64> [[MIN]] 389; 390 %a_ext = sext <2 x i32> %a to <2 x i64> 391 %cmp = icmp ult <2 x i32> %a, <i32 3, i32 3> 392 %min = select <2 x i1> %cmp, <2 x i64> <i64 2, i64 2>, <2 x i64> %a_ext 393 ret <2 x i64> %min 394} 395 396define i64 @umin_sext2(i32 %a) { 397; CHECK-LABEL: @umin_sext2( 398; CHECK-NEXT: [[A_EXT:%.*]] = sext i32 [[A:%.*]] to i64 399; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[A_EXT]], 3 400; CHECK-NEXT: [[MIN:%.*]] = select i1 [[CMP]], i64 [[A_EXT]], i64 3 401; CHECK-NEXT: ret i64 [[MIN]] 402; 403 %a_ext = sext i32 %a to i64 404 %cmp = icmp ugt i32 %a, 2 405 %min = select i1 %cmp, i64 3, i64 %a_ext 406 ret i64 %min 407} 408 409define <2 x i64> @umin_sext2_vec(<2 x i32> %a) { 410; CHECK-LABEL: @umin_sext2_vec( 411; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> [[A:%.*]] to <2 x i64> 412; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i64> [[A_EXT]], <i64 3, i64 3> 413; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 3, i64 3> 414; CHECK-NEXT: ret <2 x i64> [[MIN]] 415; 416 %a_ext = sext <2 x i32> %a to <2 x i64> 417 %cmp = icmp ugt <2 x i32> %a, <i32 2, i32 2> 418 %min = select <2 x i1> %cmp, <2 x i64> <i64 3, i64 3>, <2 x i64> %a_ext 419 ret <2 x i64> %min 420} 421 422define i64 @umax_zext(i32 %a) { 423; CHECK-LABEL: @umax_zext( 424; CHECK-NEXT: [[A_EXT:%.*]] = zext i32 [[A:%.*]] to i64 425; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[A_EXT]], 3 426; CHECK-NEXT: [[MAX:%.*]] = select i1 [[TMP1]], i64 [[A_EXT]], i64 3 427; CHECK-NEXT: ret i64 [[MAX]] 428; 429 %a_ext = zext i32 %a to i64 430 %cmp = icmp ugt i32 %a, 2 431 %max = select i1 %cmp, i64 %a_ext, i64 3 432 ret i64 %max 433} 434 435define <2 x i64> @umax_zext_vec(<2 x i32> %a) { 436; CHECK-LABEL: @umax_zext_vec( 437; CHECK-NEXT: [[A_EXT:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> 438; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i64> [[A_EXT]], <i64 3, i64 3> 439; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[TMP1]], <2 x i64> [[A_EXT]], <2 x i64> <i64 3, i64 3> 440; CHECK-NEXT: ret <2 x i64> [[MAX]] 441; 442 %a_ext = zext <2 x i32> %a to <2 x i64> 443 %cmp = icmp ugt <2 x i32> %a, <i32 2, i32 2> 444 %max = select <2 x i1> %cmp, <2 x i64> %a_ext, <2 x i64> <i64 3, i64 3> 445 ret <2 x i64> %max 446} 447 448define i64 @umin_zext(i32 %a) { 449; CHECK-LABEL: @umin_zext( 450; CHECK-NEXT: [[A_EXT:%.*]] = zext i32 [[A:%.*]] to i64 451; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[A_EXT]], 2 452; CHECK-NEXT: [[MIN:%.*]] = select i1 [[TMP1]], i64 [[A_EXT]], i64 2 453; CHECK-NEXT: ret i64 [[MIN]] 454; 455 %a_ext = zext i32 %a to i64 456 %cmp = icmp ult i32 %a, 3 457 %min = select i1 %cmp, i64 %a_ext, i64 2 458 ret i64 %min 459} 460 461define <2 x i64> @umin_zext_vec(<2 x i32> %a) { 462; CHECK-LABEL: @umin_zext_vec( 463; CHECK-NEXT: [[A_EXT:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> 464; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i64> [[A_EXT]], <i64 2, i64 2> 465; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[TMP1]], <2 x i64> [[A_EXT]], <2 x i64> <i64 2, i64 2> 466; CHECK-NEXT: ret <2 x i64> [[MIN]] 467; 468 %a_ext = zext <2 x i32> %a to <2 x i64> 469 %cmp = icmp ult <2 x i32> %a, <i32 3, i32 3> 470 %min = select <2 x i1> %cmp, <2 x i64> %a_ext, <2 x i64> <i64 2, i64 2> 471 ret <2 x i64> %min 472} 473 474; Don't crash mishandling a pattern that can't be transformed. 475 476define <2 x i16> @scalar_select_of_vectors(<2 x i16> %a, <2 x i16> %b, i8 %x) { 477; CHECK-LABEL: @scalar_select_of_vectors( 478; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 0 479; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], <2 x i16> [[A:%.*]], <2 x i16> [[B:%.*]] 480; CHECK-NEXT: ret <2 x i16> [[SEL]] 481; 482 %cmp = icmp slt i8 %x, 0 483 %sel = select i1 %cmp, <2 x i16> %a, <2 x i16> %b 484 ret <2 x i16> %sel 485} 486 487