1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -instcombine -S | FileCheck %s 3 4define i32 @t1(i16 zeroext %x, i32 %y) { 5; CHECK-LABEL: @t1( 6; CHECK-NEXT: entry: 7; CHECK-NEXT: [[CONV:%.*]] = zext i16 [[X:%.*]] to i32 8; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[Y:%.*]], 1 9; CHECK-NEXT: [[D:%.*]] = lshr i32 [[CONV]], [[TMP0]] 10; CHECK-NEXT: ret i32 [[D]] 11; 12entry: 13 %conv = zext i16 %x to i32 14 %s = shl i32 2, %y 15 %d = sdiv i32 %conv, %s 16 ret i32 %d 17} 18 19define <2 x i32> @t1vec(<2 x i16> %x, <2 x i32> %y) { 20; CHECK-LABEL: @t1vec( 21; CHECK-NEXT: entry: 22; CHECK-NEXT: [[CONV:%.*]] = zext <2 x i16> [[X:%.*]] to <2 x i32> 23; CHECK-NEXT: [[TMP0:%.*]] = add <2 x i32> [[Y:%.*]], <i32 1, i32 1> 24; CHECK-NEXT: [[D:%.*]] = lshr <2 x i32> [[CONV]], [[TMP0]] 25; CHECK-NEXT: ret <2 x i32> [[D]] 26; 27entry: 28 %conv = zext <2 x i16> %x to <2 x i32> 29 %s = shl <2 x i32> <i32 2, i32 2>, %y 30 %d = sdiv <2 x i32> %conv, %s 31 ret <2 x i32> %d 32} 33 34; rdar://11721329 35define i64 @t2(i64 %x, i32 %y) { 36; CHECK-LABEL: @t2( 37; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[Y:%.*]] to i64 38; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[X:%.*]], [[TMP1]] 39; CHECK-NEXT: ret i64 [[TMP2]] 40; 41 %1 = shl i32 1, %y 42 %2 = zext i32 %1 to i64 43 %3 = udiv i64 %x, %2 44 ret i64 %3 45} 46 47; PR13250 48define i64 @t3(i64 %x, i32 %y) { 49; CHECK-LABEL: @t3( 50; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[Y:%.*]], 2 51; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 52; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[X:%.*]], [[TMP2]] 53; CHECK-NEXT: ret i64 [[TMP3]] 54; 55 %1 = shl i32 4, %y 56 %2 = zext i32 %1 to i64 57 %3 = udiv i64 %x, %2 58 ret i64 %3 59} 60 61define i32 @t4(i32 %x, i32 %y) { 62; CHECK-LABEL: @t4( 63; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[Y:%.*]], 5 64; CHECK-NEXT: [[DOTV:%.*]] = select i1 [[TMP1]], i32 [[Y]], i32 5 65; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[X:%.*]], [[DOTV]] 66; CHECK-NEXT: ret i32 [[TMP2]] 67; 68 %1 = shl i32 1, %y 69 %2 = icmp ult i32 %1, 32 70 %3 = select i1 %2, i32 32, i32 %1 71 %4 = udiv i32 %x, %3 72 ret i32 %4 73} 74 75define i32 @t5(i1 %x, i1 %y, i32 %V) { 76; CHECK-LABEL: @t5( 77; CHECK-NEXT: [[DOTV:%.*]] = select i1 [[X:%.*]], i32 5, i32 6 78; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[V:%.*]], [[DOTV]] 79; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[Y:%.*]], i32 [[TMP1]], i32 0 80; CHECK-NEXT: ret i32 [[TMP2]] 81; 82 %1 = shl i32 1, %V 83 %2 = select i1 %x, i32 32, i32 64 84 %3 = select i1 %y, i32 %2, i32 %1 85 %4 = udiv i32 %V, %3 86 ret i32 %4 87} 88 89define i32 @t6(i32 %x, i32 %z) { 90; CHECK-LABEL: @t6( 91; CHECK-NEXT: [[X_IS_ZERO:%.*]] = icmp eq i32 [[X:%.*]], 0 92; CHECK-NEXT: [[DIVISOR:%.*]] = select i1 [[X_IS_ZERO]], i32 1, i32 [[X]] 93; CHECK-NEXT: [[Y:%.*]] = udiv i32 [[Z:%.*]], [[DIVISOR]] 94; CHECK-NEXT: ret i32 [[Y]] 95; 96 %x_is_zero = icmp eq i32 %x, 0 97 %divisor = select i1 %x_is_zero, i32 1, i32 %x 98 %y = udiv i32 %z, %divisor 99 ret i32 %y 100} 101 102; (X << C1) / X -> 1 << C1 optimizations 103 104define i32 @t7(i32 %x) { 105; CHECK-LABEL: @t7( 106; CHECK-NEXT: ret i32 4 107; 108 %shl = shl nsw i32 %x, 2 109 %r = sdiv i32 %shl, %x 110 ret i32 %r 111} 112 113; make sure the previous opt doesn't take place for wrapped shifts 114 115define i32 @t8(i32 %x) { 116; CHECK-LABEL: @t8( 117; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], 2 118; CHECK-NEXT: [[R:%.*]] = sdiv i32 [[SHL]], [[X]] 119; CHECK-NEXT: ret i32 [[R]] 120; 121 %shl = shl i32 %x, 2 122 %r = sdiv i32 %shl, %x 123 ret i32 %r 124} 125 126define <2 x i32> @t9(<2 x i32> %x) { 127; CHECK-LABEL: @t9( 128; CHECK-NEXT: ret <2 x i32> <i32 4, i32 8> 129; 130 %shl = shl nsw <2 x i32> %x, <i32 2, i32 3> 131 %r = sdiv <2 x i32> %shl, %x 132 ret <2 x i32> %r 133} 134 135define i32 @t10(i32 %x, i32 %y) { 136; CHECK-LABEL: @t10( 137; CHECK-NEXT: [[R:%.*]] = shl nsw i32 1, [[Y:%.*]] 138; CHECK-NEXT: ret i32 [[R]] 139; 140 %shl = shl nsw i32 %x, %y 141 %r = sdiv i32 %shl, %x 142 ret i32 %r 143} 144 145define <2 x i32> @t11(<2 x i32> %x, <2 x i32> %y) { 146; CHECK-LABEL: @t11( 147; CHECK-NEXT: [[R:%.*]] = shl nsw <2 x i32> <i32 1, i32 1>, [[Y:%.*]] 148; CHECK-NEXT: ret <2 x i32> [[R]] 149; 150 %shl = shl nsw <2 x i32> %x, %y 151 %r = sdiv <2 x i32> %shl, %x 152 ret <2 x i32> %r 153} 154 155define i32 @t12(i32 %x) { 156; CHECK-LABEL: @t12( 157; CHECK-NEXT: ret i32 4 158; 159 %shl = shl nuw i32 %x, 2 160 %r = udiv i32 %shl, %x 161 ret i32 %r 162} 163 164; make sure the previous opt doesn't take place for wrapped shifts 165 166define i32 @t13(i32 %x) { 167; CHECK-LABEL: @t13( 168; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], 2 169; CHECK-NEXT: [[R:%.*]] = udiv i32 [[SHL]], [[X]] 170; CHECK-NEXT: ret i32 [[R]] 171; 172 %shl = shl i32 %x, 2 173 %r = udiv i32 %shl, %x 174 ret i32 %r 175} 176 177define <2 x i32> @t14(<2 x i32> %x) { 178; CHECK-LABEL: @t14( 179; CHECK-NEXT: ret <2 x i32> <i32 4, i32 8> 180; 181 %shl = shl nuw <2 x i32> %x, <i32 2, i32 3> 182 %r = udiv <2 x i32> %shl, %x 183 ret <2 x i32> %r 184} 185 186define i32 @t15(i32 %x, i32 %y) { 187; CHECK-LABEL: @t15( 188; CHECK-NEXT: [[R:%.*]] = shl nuw i32 1, [[Y:%.*]] 189; CHECK-NEXT: ret i32 [[R]] 190; 191 %shl = shl nuw i32 %x, %y 192 %r = udiv i32 %shl, %x 193 ret i32 %r 194} 195 196define <2 x i32> @t16(<2 x i32> %x, <2 x i32> %y) { 197; CHECK-LABEL: @t16( 198; CHECK-NEXT: [[R:%.*]] = shl nuw <2 x i32> <i32 1, i32 1>, [[Y:%.*]] 199; CHECK-NEXT: ret <2 x i32> [[R]] 200; 201 %shl = shl nuw <2 x i32> %x, %y 202 %r = udiv <2 x i32> %shl, %x 203 ret <2 x i32> %r 204} 205