1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -instcombine -S | FileCheck %s 3 4; int test0(int a) { return (a + (~(a & 0x55555555) + 1)); } 5define i32 @test0(i32 %a0) { 6; CHECK-LABEL: @test0( 7; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A0:%.*]], -1431655766 8; CHECK-NEXT: ret i32 [[TMP1]] 9; 10 %1 = and i32 %a0, 1431655765 11 %2 = xor i32 %1, -1 12 %3 = add nsw i32 %2, 1 13 %4 = add nsw i32 %a0, %3 14 ret i32 %4 15} 16 17define <4 x i32> @test0_vec(<4 x i32> %a0) { 18; CHECK-LABEL: @test0_vec( 19; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[A0:%.*]], <i32 -1431655766, i32 -1431655766, i32 -1431655766, i32 -1431655766> 20; CHECK-NEXT: ret <4 x i32> [[TMP1]] 21; 22 %1 = and <4 x i32> %a0, <i32 1431655765, i32 1431655765, i32 1431655765, i32 1431655765> 23 %2 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1> 24 %3 = add nsw <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1> 25 %4 = add nsw <4 x i32> %a0, %3 26 ret <4 x i32> %4 27} 28 29; int test1(int a) { return (a + (~((a >> 1) & 0x55555555) + 1)); } 30define i32 @test1(i32 %a0) { 31; CHECK-LABEL: @test1( 32; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[A0:%.*]], 1 33; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 1431655765 34; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[A0]], [[TMP2]] 35; CHECK-NEXT: ret i32 [[TMP3]] 36; 37 %1 = ashr i32 %a0, 1 38 %2 = and i32 %1, 1431655765 39 %3 = xor i32 %2, -1 40 %4 = add nsw i32 %3, 1 41 %5 = add nsw i32 %a0, %4 42 ret i32 %5 43} 44 45define <4 x i32> @test1_vec(<4 x i32> %a0) { 46; CHECK-LABEL: @test1_vec( 47; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> [[A0:%.*]], <i32 1, i32 1, i32 1, i32 1> 48; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[TMP1]], <i32 1431655765, i32 1431655765, i32 1431655765, i32 1431655765> 49; CHECK-NEXT: [[TMP3:%.*]] = sub <4 x i32> [[A0]], [[TMP2]] 50; CHECK-NEXT: ret <4 x i32> [[TMP3]] 51; 52 %1 = ashr <4 x i32> %a0, <i32 1, i32 1, i32 1, i32 1> 53 %2 = and <4 x i32> %1, <i32 1431655765, i32 1431655765, i32 1431655765, i32 1431655765> 54 %3 = xor <4 x i32> %2, <i32 -1, i32 -1, i32 -1, i32 -1> 55 %4 = add nsw <4 x i32> %3, <i32 1, i32 1, i32 1, i32 1> 56 %5 = add nsw <4 x i32> %a0, %4 57 ret <4 x i32> %5 58} 59